Semiconductor apparatus and semiconductor memory apparatus

Abstract

A semiconductor apparatus includes a temperature detecting circuit and a temperature raising circuit. The temperature detecting circuit detects a temperature to generate temperature detection information. The temperature raising circuit generates heat through a toggling operation based on the temperature detection information.

What is claimed is: 
     
         1 . A semiconductor apparatus comprising:
 a temperature detecting circuit configured to detect a temperature to generate temperature detection information; and   a temperature raising circuit configured to generate heat through a toggling operation based on the temperature detection information.   
     
     
         2 . The semiconductor apparatus of  claim 1 , wherein the temperature detecting circuit is configured to activate the temperature detection information by comparing the temperature with a reference temperature. 
     
     
         3 . The semiconductor apparatus of  claim 1 , wherein the temperature raising circuit is configured to generate a heating clock signal that toggles according to the temperature detection information. 
     
     
         4 . The semiconductor apparatus of  claim 3 , wherein the temperature raising circuit includes:
 an oscillating circuit configured to generate the heating clock signal through an oscillating operation; and   an activating circuit configured to activate the oscillating operation based on the temperature detection information.   
     
     
         5 . The semiconductor apparatus of  claim 3 , further comprising a transferring line configured to transfer the heating clock signal to an internal circuit. 
     
     
         6 . The semiconductor apparatus of  claim 3 ,
 wherein the temperature detection information includes a signal of a code type corresponding to the temperature, and   wherein the temperature raising circuit is configured to to generate the heating clock signal that toggles at different frequencies from each other according to the temperature detection information of the code type.   
     
     
         7 . The semiconductor apparatus of  claim 1 , wherein the temperature detection information is activated regardless of the temperature in an initial drive interval. 
     
     
         8 . A semiconductor memory apparatus comprising:
 a command decoding circuit configured to generate an internal refresh command signal based on an external command signal;   a temperature detecting circuit configured to detect a temperature to generate temperature detection information;   a refresh control circuit configured to generate a refresh control signal, which toggles at a first frequency, based on the internal refresh command signal during a refresh operation and configured to generate the refresh control signal, which toggles at a second frequency higher than the first frequency, based on the temperature detection information during a heating operation; and   a memory bank circuit configured to perform a refresh operation based on the refresh control signal,   wherein the refresh control circuit is configured to generate heat through a toggling operation.   
     
     
         9 . The semiconductor memory apparatus of  claim 8 , wherein the refresh control circuit includes:
 a first oscillating circuit configured to generate the refresh control signal having the second frequency based on the temperature detection information and generate the refresh control signal having the second frequency; and   a second oscillating circuit configured to generate the refresh control signal having the first frequency based on the internal refresh command signal.   
     
     
         10 . The semiconductor memory apparatus of  claim 8 , further comprising a transferring line configured to transfer the refresh control signal to the memory bank circuit. 
     
     
         11 . A semiconductor memory apparatus comprising:
 a temperature detecting circuit configured to detect a temperature to generate temperature detection information;   a heating control circuit configured to provide, based on the temperature detection information, a command control signal and a heating data signal that toggles; and   a memory bank circuit configured to store therein the heating data signal based on the command control signal,   wherein the memory bank circuit is configured to generate heat through a toggling operation.   
     
     
         12 . The semiconductor memory apparatus of  claim 11 ,
 wherein the command control signal includes a write control signal, and   wherein the memory bank circuit is configured to perform a write operation of storing therein the heating data signal based on the write control signal.   
     
     
         13 . The semiconductor memory apparatus of  claim 12 , wherein the heating control circuit includes:
 a write control circuit configured to generate the write control signal based on the temperature detection information; and   a data providing circuit configured to provide, based on the temperature detection information, the heating data signal to the memory bank circuit.   
     
     
         14 . The semiconductor memory apparatus of  claim 11 ,
 wherein the command control signal includes read and write (read/write) control signals,   wherein the memory bank circuit is configured to perform, based on the read control signal, a read operation of reading out data stored in the memory bank circuit, and   wherein the memory bank circuit is configured to perform, based on the write control signal, a write operation of storing into the memory bank circuit the heating data signal, which is inverted from the read-out data from the memory bank circuit.   
     
     
         15 . The semiconductor memory apparatus of  claim 14 , wherein the heating control circuit includes:
 a read/write control circuit configured to generate the read/write control signals based on the temperature detection information; and   a data inverting circuit configured to generate, based on the temperature detection information, the heating data signal, which is inverted from the read-out data from the memory bank circuit.   
     
     
         16 . The semiconductor memory apparatus of  claim 14 , wherein, in an inversion write mode, a pair of the read operation on the data stored in the memory bank circuit and the write operation on the heating data signal is performed an even number of times.