Semiconductor device and semiconductor memory device

Abstract

A semiconductor device of an embodiment includes a first electrode, a second electrode, a first metallic region provided between the first electrode and the second electrode and includes at least one metallic element selected from the group consisting of indium (In), gallium (Ga), zinc (Zn), aluminum (Al), magnesium (Mg), manganese (Mn), titanium (Ti), tungsten (W), molybdenum (Mo), and tin (Sn), a second metallic region provided between the first metallic region and the second electrode and includes the at least one metallic element, a semiconductor region provided between the first metallic region and the second metallic region and includes the at least one metallic element and oxygen (O), an insulating region provided between the first metallic region and the second metallic region and is surrounded by the semiconductor region, a gate electrode surrounding the semiconductor region, and a gate insulating layer provided between the semiconductor region and the gate electrode.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a first electrode;   a second electrode;   a first oxide semiconductor region provided between the first electrode and the second electrode, the first oxide semiconductor region including at least one predetermined element selected from the group consisting of indium (In), silicon (Si), and tin (Sn);   a second oxide semiconductor region provided between the first oxide semiconductor region and the second electrode, the second oxide semiconductor region including the at least one predetermined element;   a third oxide semiconductor region provided between the first oxide semiconductor region and the second oxide semiconductor region, the third oxide semiconductor region including or not including the at least one predetermined element, the third oxide semiconductor region having a concentration of the at least one predetermined element lower than a concentration of the at least one predetermined element in the first oxide semiconductor region and the second oxide semiconductor region, the third oxide semiconductor region including a first portion and a second portion surrounded by the first portion, and a first distance between the first oxide semiconductor region and the second oxide semiconductor region between which the first portion is sandwiched is different from a second distance between the first oxide semiconductor region and the second oxide semiconductor region between which the second portion is sandwiched;   a gate electrode surrounding the third oxide semiconductor region; and   a gate insulating layer provided between the third oxide semiconductor region and the gate electrode.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the first distance is smaller than the second distance. 
     
     
         3 . The semiconductor device according to  claim 1 , wherein the concentration of the at least one predetermined element in the first oxide semiconductor region and the second oxide semiconductor region is equal to or higher than 1×10 17  cm −3  and is equal to or lower than 1×10 21  cm −3 . 
     
     
         4 . The semiconductor device according to  claim 1 , wherein the third oxide semiconductor region and the first electrode are spaced apart from each other, and the third oxide semiconductor region and the second electrode are spaced apart from each other. 
     
     
         5 . The semiconductor device according to  claim 1 , wherein the first oxide semiconductor region, the second oxide semiconductor region, and the third semiconductor region include indium (In), gallium (Ga), and zinc (Zn). 
     
     
         6 . A semiconductor device comprising:
 a first electrode;   a second electrode;   a first oxide semiconductor region provided between the first electrode and the second electrode;   a second oxide semiconductor region provided between the first oxide semiconductor region and the second electrode;   a third oxide semiconductor region provided between the first oxide semiconductor region and the second oxide semiconductor region, the third oxide semiconductor region having electrical resistance higher than electrical resistances of the first oxide semiconductor region and the second oxide semiconductor region, and the third oxide semiconductor region including a first portion and a second portion surrounded by the first portion;   a gate electrode surrounding the third oxide semiconductor region; and   a gate insulating layer provided between the third oxide semiconductor region and the gate electrode,   wherein a first distance between the first electrode and the first portion between which the first oxide semiconductor region is sandwiched is larger than a second distance between the first electrode and the second portion between which the first oxide semiconductor region is sandwiched.   
     
     
         7 . The semiconductor device according to  claim 6 , wherein a third distance between the second electrode and the first portion between which the second oxide semiconductor region is sandwiched is larger than a fourth distance between the second electrode and the second portion between which the second oxide semiconductor region is sandwiched. 
     
     
         8 . The semiconductor device according to  claim 6 , wherein the third oxide semiconductor region and the first electrode are spaced apart from each other, and the third oxide semiconductor region and the second electrode are spaced apart from each other. 
     
     
         9 . The semiconductor device according to  claim 6 , wherein the first oxide semiconductor region and the second oxide semiconductor region include at least one predetermined element selected from the group consisting of indium (In), silicon (Si), and tin (Sn). 
     
     
         10 . The semiconductor device according to  claim 6 , wherein the first oxide semiconductor region, the second oxide semiconductor region, and the third semiconductor region include indium (In), gallium (Ga), and zinc (Zn).