Integrated circuit including signal line and power line and method of designing the same

Abstract

An integrated circuit (IC) includes: a plurality of gate electrodes extending in a first direction and arranged in a second direction that is orthogonal to the first direction; a plurality of first power lines extending in the first direction to supply power to the standard cell, and respectively placed to be adjacent to first sides of the gate electrodes; and a plurality of signal lines extending in the first direction to transfer an input signal or an output signal of the standard cell, and respectively placed to be adjacent to second sides of the gate electrodes.

1 . An integrated circuit (IC) comprising a standard cell, the IC comprising:
 a plurality of gate electrodes extending in a first direction and arranged in a second direction that is orthogonal to the first direction;   a plurality of first power lines extending in the first direction to supply power to the standard cell, and respectively placed to be adjacent to first sides of the gate electrodes; and   a plurality of signal lines extending in the first direction to transfer an input signal or an output signal of the standard cell, and respectively placed to be adjacent to second sides of the gate electrodes.   
     
     
         2 . The IC of  claim 1 , further comprising a plurality of second power lines extending in the second direction to supply power to the standard cell, placed in a wiring layer below or above a wiring layer in which the first power lines are placed, and connected to the first power lines. 
     
     
         3 . The IC of  claim 2 , wherein the signal lines and the first power lines are placed in a same wiring layer. 
     
     
         4 . The IC of  claim 1 , wherein the signal lines and the first power lines are alternately placed in the second direction. 
     
     
         5 . The IC of  claim 4 , wherein the signal lines and the first power lines are not placed on the gate electrodes. 
     
     
         6 . The IC of  claim 1 , wherein the gate electrodes are arranged in the second direction at a first pitch,
 wherein the signal lines and the first power lines are arranged in the second direction at a second pitch, and   wherein the first pitch is greater than the second pitch.   
     
     
         7 . The IC of  claim 6 , wherein the first pitch is double the second pitch. 
     
     
         8 . The IC of  claim 6 , wherein a leftmost gate electrode among the gate electrodes is separated from a left boundary of the standard cell by a first offset in the second direction,
 wherein a leftmost signal line among the signal lines or a leftmost first power line among the first power lines is separated from the left boundary of the standard cell by a second offset in the second direction,   wherein the first offset is the same as the first pitch, and   wherein the second offset is the same as the second pitch.   
     
     
         9 . The IC of  claim 1 , further comprising a cell separation structure by which the standard cell is separated from another standard cell adjacent to the standard cell in the second direction,
 wherein at least one of the first power lines is placed to be adjacent to a second side of the cell separation structure, and   wherein at least one of the signal lines is placed to be adjacent to a first side of the cell separation structure.   
     
     
         10 . An integrated circuit (IC) comprising a plurality of standard cells, the IC comprising:
 a plurality of gate electrodes aligned along a plurality of first tracks extending in a first direction and arranged in a second direction orthogonal to the first direction;   at least one signal line aligned along at least one second track, respectively, located at a pre-defined side of at least one of the gate electrodes, among a plurality of second tracks extending in the first direction and arranged in the second direction, to transfer an input signal or an output signal of the standard cells; and   at least one first power line aligned along at least one of the second tracks except the second track located at the pre-defined side, to supply power to the standard cells.   
     
     
         11 . The IC of  claim 10 , wherein the signal line and the first power line do not overlap the gate electrodes. 
     
     
         12 . The IC of  claim 10 , further comprising a plurality of second power lines extending in the second direction to supply power to the standard cells,
 wherein the first power line is formed in a wiring layer located higher than the second power lines.   
     
     
         13 . The IC of  claim 10 , wherein the gate electrodes are arranged in the second direction at a first pitch,
 wherein the signal line and the first power line are separated from each other in the second direction by a second pitch, and   wherein the first pitch is greater than the second pitch.   
     
     
         14 . The IC of  claim 13 , wherein the first power line comprises a plurality first power lines arranged in the second direction at double the second pitch. 
     
     
         15 . The IC of  claim 10 , further comprising a cell separation structure by which the standard cell is separated from another standard cell adjacent to the standard cell in the second direction,
 wherein a first track, adjacent to the cell separation structure, among the first tracks is separated from the cell separation structure by a first offset in the second direction, and   wherein a second track, adjacent to the cell separation structure, among the second tracks is separated from the cell separation structure by a second offset in the second direction   
     
     
         16 - 20 . (canceled) 
     
     
         21 . An integrated circuit (IC) comprising a semiconductor cell, the semiconductor cell comprising:
 a plurality gate electrodes arranged in a first direction on a substrate;   a plurality power lines disposed at a plurality of first sides, respectively, of the gate electrodes in parallel with the gate electrodes, and configured to transfer power to the semiconductor cell; and   a plurality signal lines disposed at a plurality second sides, respectively, of the gate electrodes in parallel with the gate electrodes, and configured to transfer an input signal or an output signal of the semiconductor cell,   wherein the first sides and the second side are positioned at left sides and right sides of the gate electrodes, respectively, or right sides and left sides of the gate electrodes, respectively.   
     
     
         22 . The IC of  claim 21 , further comprising a cell separation structure disposed at a left or right end of the semiconductor cell in parallel with the gate electrodes to separate the semiconductor cell from an adjacent semiconductor cell,
 wherein a first offset between the cell separation structure and a leftmost or rightmost gate electrode, among the gate electrodes, is the same as a first pitch at which the gate electrodes are arranged in a horizontal direction, and   wherein at least one of the power lines and at least one of the signal lines are disposed between the cell separation structure and the leftmost or rightmost gate electrode.   
     
     
         23 . The IC of  claim 22 , wherein one of the first power line and the signal line disposed closer to the cell separation structure among the first power line and the signal line is separated from the cell separation structure by a second offset, and
 wherein the second offset is the same as a second pitch at the power lines and the signal lines are arranged in the horizontal direction.   
     
     
         24 . The IC of  claim 23 , wherein the first offset is greater than the second offset. 
     
     
         25 . The IC of  claim 22 , further comprising another cell separation structure disposed at the left or right end of the semiconductor cell with the gate electrodes therebetween,
 wherein the other cell separation structure is separated from the leftmost or rightmost gate electrode by the first offset, and   wherein another at least one of the power lines and another at least one of the signal lines are disposed between the other cell separation structure and the leftmost or rightmost gate electrode.