Method for selective etching of nanostructures

Abstract

The present invention relates to a method for selective etching of a nanostructure (10). The method comprising: providing the nanostructure (10) having a main surface (12) delimited by, in relation to the main surface (12), inclined surfaces (14); and subjecting the nanostructure (10) for a dry etching, wherein the dry etching comprises: subjecting the nanostructure (10) for a low energy particle beam (20) having a direction perpendicular to the main surface (12); whereby a recess (16) in the nanostructure (10) is formed, the recess (16) having its opening at the main surface (12) of the nanostructure (10).

What is claimed is: 
     
         1 . A nanostructure formed by:
 providing a substrate having a first layer and a resist layer, wherein the first layer is between the resist layer and the substrate;   lithography patterning the resist layer, thereby exposing areas of the first layer;   etching the exposed areas of the first layer, thereby forming first recesses in the first layer;   removing the remaining resist layer, thereby forming ridges of the first layer between the first recesses of the first layer;   subjecting the first layer to a first dry etching process comprising subjecting the first layer to a particle beam whereby selective etching of the ridges of the first layer relative to walls of the first recesses in the layer is achieved such that second recesses in the first layer are formed, the second recesses in the first layer having openings at the ridges of the first layer.   
     
     
         2 . The nanostructure according to  claim 1 , being comprised in a transistor gate channel. 
     
     
         3 . The nanostructure according to  claim 1 , being comprised in a nanowire gate-all-around field effect transistor. 
     
     
         4 . A nanostructure formed by:
 providing a substrate having a first layer, a second layer, a resist layer and a hardmask layer, wherein the first layer is between the resist layer and the hardmask layer, wherein the hardmask layer is arranged in between the first and second layers;   lithography patterning the resist layer, thereby exposing areas of the first layer;   etching the exposed areas of the first layer, thereby forming first recesses in the first layer;   removing the remaining resist layer, thereby forming ridges of the first layer between the first recesses of the first layer;   
       subjecting the first layer to a first dry etching process comprising subjecting the first layer to a particle beam whereby selective etching of the ridges of the first layer relative to walls of the first recesses in the layer is achieved such that second recesses in the first layer are formed, the second recesses in the first layer having openings at the ridges of the first layer,
 wherein etching the exposed areas of the first layer and subjecting the first layer to the dry etching are performed such that the hardmask layer is exposed, 
 removing the hardmask layer between the first fins, thereby exposing areas of the second layer; 
 etching the exposed areas of the second layer, thereby forming first recesses in the second layer; 
 removing the first fins and the remaining hardmask layer, thereby forming ridges of the second layer between the first recesses in the second layer; 
 subjecting the second layer to a second dry etching process comprising subjecting the second layer to a particle beam, whereby selective etching of the ridges of the second layer relative to walls of the first recesses in the second layer is achieved such that second recesses in the second layer are formed, the second recesses having openings at the ridges of the second layer. 
 
     
     
         5 . The nanostructure according to  claim 4 , being comprised in a transistor gate channel. 
     
     
         6 . The nanostructure according to  claim 4 , being comprised in a nanowire gate-all-around field effect transistor.