Memory device with increased electrode resistance to reduce transient selection current

Abstract

A memory cell design is disclosed. The design is particularly well-suited for three-dimensional cross-point (3D X-point) memory configurations. Various embodiments of the memory cell design include one or more electrodes having an increased resistance compared to existing memory cell designs or compared to other electrodes within a same memory cell. A memory device includes an array of memory cells with each memory cell arranged between a word line and a bit line of the memory device. Some embodiments include additional material layers to increase memory cell resistance. Some embodiments include electrodes having an increased thickness to increase the resistance. Some embodiments include electrodes having a composition with a higher resistivity. Some embodiments include electrodes with increased interface resistance. Some embodiments include a combination of such features. In any case, the resulting increased memory cell resistance causes a reduction in the transient selection current for the given memory cell.

1 - 20 . (canceled) 
     
     
         21 . A memory device, comprising:
 an array of memory cells, each memory cell arranged between a word line and a bit line of the memory device, each memory cell to include:
 a stack of layers to include a phase change layer, a selector layer, and a plurality of intermediate electrodes; and 
 an interface layer in direct contact with a first intermediate electrode of the plurality of intermediate electrodes, wherein a combined resistance of the first intermediate electrode and the interface layer is at least 20% higher than a resistance of one or more of the other intermediate electrodes of the plurality of intermediate electrodes. 
   
     
     
         22 . The memory device of  claim 21 , the interface layer comprising one or more of tungsten, silicon, aluminum, oxygen, boron, or nitrogen. 
     
     
         23 . The memory device of  claim 21 , wherein the first intermediate electrode has a thickness that is up to 50% greater than a thickness of each of the one or more other intermediate electrodes. 
     
     
         24 . The memory device of  claim 21 , wherein the interface layer has a thickness between about 20 Å and about 50 Å. 
     
     
         25 . The memory device of  claim 21 , wherein one or more of the plurality of intermediate electrodes comprises carbon and nitrogen. 
     
     
         26 . The memory device of  claim 21 , wherein the first intermediate electrode is beneath the selector layer, and the plurality of intermediate electrodes further comprises one or both of:
 a second intermediate electrode between the phase change layer and the selector layer; and   a third intermediate electrode above the phase change layer.   
     
     
         27 . The memory device of  claim 21 , wherein the phase change layer includes a chalcogenide material. 
     
     
         28 . An electronic device comprising:
 a chip package; and   a memory device included in the chip package, the memory device comprising:
 an array of memory cells, each memory cell arranged between a word line and a bit line of the memory device, each memory cell to include:
 a stack of layers to include a phase change layer, a selector layer, and a plurality of intermediate electrodes; and 
 an interface layer in direct contact with a first intermediate electrode of the plurality of intermediate electrodes, wherein a combined resistance of the first intermediate electrode and the interface layer is at least 20% higher than a resistance of one or more of the other intermediate electrodes of the plurality of intermediate electrodes. 
 
   
     
     
         29 . The electronic device of  claim 28 , the interface layer comprising one or more of tungsten, silicon, aluminum, oxygen, boron, or nitrogen. 
     
     
         30 . The electronic device of  claim 28 , wherein the first intermediate electrode has a thickness that is up to 50% greater than a thickness of each of the one or more other intermediate electrodes. 
     
     
         31 . electronic device of  claim 28 , wherein the interface layer has a thickness between about 20 Å and about 50 Å. 
     
     
         32 . electronic device of  claim 28 , wherein one or more of the plurality of intermediate electrodes comprises carbon and nitrogen. 
     
     
         33 . electronic device of  claim 28 , wherein the first intermediate electrode is beneath the selector layer, and the plurality of intermediate electrodes further comprises one or both of:
 a second intermediate electrode between the phase change layer and the selector layer; and   a third intermediate electrode above the phase change layer.   
     
     
         34 . electronic device of  claim 28 , wherein the phase change layer includes a chalcogenide material.