Formation of bottom isolation

Abstract

A semiconductor structure may include a source, a drain, a plurality of nanowire channels between the source and the drain, and a bottom insulation layer. The plurality of nanowire channels may each have a width defined by the source and drain. The bottom insulation layer may contact a bottom nanowire channel of the plurality of nanowire channels and may be disposed between the source and drain. The bottom insulation layer may have a width no greater than the width of the bottom nanowire channel.

1 . A semiconductor structure, comprising:
 a source;   a drain;   a plurality of nanowire channels between the source and the drain, the plurality of nanowire channels each having a width defined by the source and drain; and   a bottom insulation layer, wherein the bottom insulation layer contacts a bottom nanowire channel of the plurality of nanowire channels and is disposed between the source and drain, and wherein the bottom insulation layer has a width no greater than the width of the bottom nanowire channel.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the source, the drain, and the bottom insulation layer are disposed over a silicon-containing substrate. 
     
     
         3 . The semiconductor structure of  claim 2 , wherein the source and the drain are epitaxially grown over the silicon-containing substrate. 
     
     
         4 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer has a width-to-thickness aspect ratio ranging between about 2:1 and 20:1. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer comprises an oxide material. 
     
     
         6 . The semiconductor structure of  claim 1 , further comprising a plurality of gate structures, wherein the plurality of gate structures are each disposed around a nanowire channel of at least some of the plurality of nanowire channels. 
     
     
         7 . The semiconductor structure of  claim 6 , wherein a ratio of a thickness of the bottom insulation layer to a thickness of each of the plurality of gate structures is between about 4:1 and about 1:5. 
     
     
         8 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer is characterized by a width of between about 10 nm and about 100 nm. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer is characterized by a thickness of between about 5 nm and about 25 nm. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein a ratio of a thickness of the bottom insulation layer to a thickness of each of the plurality of nanowire channels is between about 4:1 and about 1:5. 
     
     
         11 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer does not extend to the source or the drain. 
     
     
         12 . The semiconductor structure of  claim 1 , wherein the bottom insulation layer comprises silicon oxide. 
     
     
         13 . The semiconductor structure of  claim 1 , wherein the source, the drain, or both comprise silicon material. 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the silicon material comprises phosphorous doped silicon, silicon germanium, or boron doped silicon germanium. 
     
     
         15 . A semiconductor structure, comprising:
 a source;   a drain;   a plurality of nanowire channels between the source and the drain, the plurality of nanowire channels each having a width defined by the source and drain; and   a bottom insulation layer, wherein the bottom insulation layer contacts a bottom nanowire channel of the plurality of nanowire channels, wherein the bottom insulation layer has a width no greater than the width of the bottom nanowire channel, and wherein the bottom insulation layer is formed without conducting a reactive-ion etching method or an ion implantation method.   
     
     
         16 . The semiconductor structure of  claim 15 , wherein the bottom insulation layer is disposed between the source and drain. 
     
     
         17 . The semiconductor structure of  claim 15 , wherein the source and the drain are epitaxially grown over a silicon-containing substrate. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein the silicon-containing substrate is free of damage due to reactive-ion etching or ion implantation. 
     
     
         19 . A semiconductor structure, comprising:
 a source epitaxially grown over a silicon-containing substrate;   a drain epitaxially grown over the silicon-containing substrate;   a plurality of nanowire channels between the source and the drain, the plurality of nanowire channels each having a width defined by the source and drain; and   a bottom insulation layer, wherein the bottom insulation layer is disposed between the silicon-containing substrate and a bottom nanowire channel of the plurality of nanowire channels, wherein the bottom insulation layer is disposed between the source and drain, wherein the bottom insulation layer has a width no greater than the width of the bottom nanowire channel.   
     
     
         20 . The semiconductor structure of  claim 19 , wherein the bottom insulation layer is characterized by a width substantially the same as the width of each of the plurality of nanowire channels.