Semiconductor integrated circuit device

Abstract

A layout structure of a standard cell using vertical nanowire (VNW) FETs is provided. A p-type transistor region in which VNW FETs are formed and an n-type transistor region in which VNW FETs are formed are provided between a power supply interconnect VDD and a power supply interconnect VSS. A local interconnect is placed across the p-type transistor region and the n-type transistor region. The top electrode of a transistor that is a dummy VNW FET is connected with the local interconnect.

What is claimed is: 
     
         1 . A semiconductor integrated circuit device comprising:
 a circuit block having a plurality of cell rows each including a plurality of standard cells lining up in a first direction, the cell rows being arranged in a second direction perpendicular to the first direction,   
       wherein
 the circuit block includes
 a first power supply interconnect extending in the first direction, and 
 first and second cell rows, which are part of the plurality of cell rows, placed on both sides of the first power supply interconnect in the second direction, the first and second cell rows sharing the first power supply interconnect, 
 
 the first cell row includes a first standard cell having a first vertical nanowire (VNW) FET, 
 the second cell row includes a second standard cell having a second VNW FET, 
 the first VNW FET and the second VNW FET are placed at the same position in the first direction, and 
 the first power supply interconnect is connected with at least either a top electrode or bottom electrode of the first VNW FET and connected with at least either a top electrode or bottom electrode of the second VNW FET. 
 
     
     
         2 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first power supply interconnect is connected with the top electrode of the first VNW FET and the top electrode of the second VNW FET.   
     
     
         3 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first power supply interconnect is connected with the bottom electrode of the first VNW FET and the bottom electrode of the second VNW FET.   
     
     
         4 . The semiconductor integrated circuit device of  claim 1 , wherein
 the first power supply interconnect is connected with the top electrode of the first VNW FET and the bottom electrode of the second VNW FET.