Raised pad formations for contacts in three-dimensional structures on microelectronic workpieces

Abstract

Embodiments provide raised pad formations for step contacts in three-dimensional structures formed on microelectronic workpieces. Steps are formed in a multilayer stack that is used for the three-dimensional structure. The multilayer stack includes alternating non-conductive and conductive layers. For one embodiment, alternating oxide and polysilicon layers are used. The steps expose contact regions on different conductive layers. Material layers are formed on the contact regions to form raised pads. The material layers preferably have a high selectivity with respect to the non-conductive material for etch processes. A protective layer is formed over the steps and the raised pads, and contact holes are formed through the protective layer to the raised pads. Contacts are then formed within the contact holes. The raised pads inhibit punch-through of the non-conductive layers during the forming of the contact holes thereby improving performance of resulting devices formed in the microelectronic workpieces.

What is claimed is: 
     
         1 . A structure formed on a microelectronic workpiece, comprising:
 a multilayer stack comprising alternating non-conductive layers and conductive layers;   steps formed in the multilayer stack to form contact regions on different conductive layers;   Ruthenium (Ru) material layers formed on the contact regions to provide raised pads;   an oxide protective layer formed over the steps and the raised pads; and   contacts formed through the protective layer to the raised pads;   wherein punch-through of the non-conductive layers is inhibited by the raised pads.   
     
     
         2 . The structure of  claim 1 , wherein the alternating non-conductive layers and conductive layers comprise oxide layers and polysilicon layers. 
     
     
         3 . The structure of  claim 1 , wherein the multilayer stack is part of a three-dimensional memory structure formed on the microelectronic workpiece. 
     
     
         4 . The structure of  claim 1 , wherein the non-conductive layers comprise oxide layers. 
     
     
         5 . The structure of  claim 1 , wherein the protective layer comprises an oxide layer. 
     
     
         6 . The structure of  claim 1 , wherein the non-conductive layers comprise oxide layers, wherein the protective layer comprises an oxide layer, and wherein the material layers have an etch selectivity to oxide such that an etch rate for oxide is at least five hundred times or greater than an etch rate for the material layers. 
     
     
         7 . The structure of  claim 1 , wherein the contact extends to a surface of the raised pad. 
     
     
         8 . The structure of  claim 1 , wherein the contact extends at least partially through the raised pad. 
     
     
         9 . The structure of  claim 1 , wherein the contact extends through the raised pad to a surface of one of the layers of The multilayer stack. 
     
     
         10 . The structure of  claim 1 , wherein the contact extends through the raised pad and at least partially through the one of the layers of the multilayered stack. 
     
     
         11 . A structure formed on a microelectronic workpiece, comprising:
 a multilayer stack comprising alternating non-conductive layers and conductive layers;   steps formed in the multilayer stack to form contact regions on different conductive layers;   material layers formed on the contact regions to provide raised pads;   an oxide protective layer formed over the steps and the raised pads; and   contacts formed through the protective layer to the raised pads;   wherein punch-through of the non-conductive layers is inhibited by the raised pads and the oxide has an etch rate when exposed to an etchant comprising carbon-fluoride based chemistry that is at least five hundred times or greater than an etch rate for the material layers when exposed to an etchant comprising carbon-fluoride based chemistry.   
     
     
         12 . The structure of  claim 11 , wherein the alternating non-conductive layers and conductive layers comprise oxide layers and polysilicon layers. 
     
     
         13 . The structure of  claim 11 , wherein the multilayer stack is part of a three-dimensional memory structure formed on the microelectronic workpiece. 
     
     
         14 . The structure of  claim 11 , wherein the non-conductive layers comprise oxide layers. 
     
     
         15 . The structure of  claim 11 , wherein the material layers comprise a metal-oxide including at least one of AlO, TiO, SnO, SiN, SiCN, TiN, AlN, or TaN. 
     
     
         16 . The structure of  claim 11 , wherein the material layers comprise a metal including at least one of Ru, Mo, W, Ti, Ta, Co, or Ni. 
     
     
         17 . The structure of  claim 11 , wherein the contact extends to a surface of the raised pad. 
     
     
         18 . The structure of  claim 11 , wherein the contact extends at least partially through the raised pad. 
     
     
         19 . The structure of  claim 11 , wherein the contact extends through the raised pad to a surface of one of the layers of the multilayer stack. 
     
     
         20 . The structure of  claim 11 , wherein the contact extends through the raised pad and at least partially through the one of the layers of the multilayered stack.