Trench-gate transistor with gate dielectric having a first thickness between the gate electrode and the channel region and a second greater thickness between the gate electrode and the source/drain regions

Abstract

The present disclosure provides a transistor, a transistor forming method thereof, and a semiconductor device. The transistor forming method comprises providing a substrate, the substrate comprising a first region for forming a source region and a second region for forming a drain region; forming a gate groove in the substrate to separate the first region and the second region, a part of the substrate along the bottom of the gate groove being used for constituting an embedded channel region of a transistor; forming a gate dielectric layer on the gate groove of the substrate to cover the embedded channel region and to extend to cover a side of the first region and a side of the second region in the gate groove; and forming a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove.

What is claimed is: 
     
         1 . A transistor, comprising:
 a substrate, a source region and a drain region in the substrate, a gate groove between the source region and the drain region formed in the substrate, a bottom of the gate groove in the substrate located lower than the source region and the drain region to constitute an embedded channel region of the transistor;   a gate dielectric layer covering a part of the substrate corresponds to the embedded channel region and extending to cover a side of the source region and a side of the drain region in the gate groove, wherein a part of the gate dielectric layer that covers the channel region constitutes a first portion of the gate dielectric layer, a part of the gate dielectric layer that covers the sides of the source region and the drain region in the gate groove constitutes a second portion of the gate dielectric layer, the gate groove comprising a first part and a second part on the first part, the first part corresponding to the first portion of the gate dielectric layer, the second part corresponding to the second portion of the gate dielectric layer, and an average thickness of the second portion of the gate dielectric layer is greater than an average thickness of the first portion of the gate dielectric layer, wherein a depth of the second portion of the gate dielectric layer, measured from a top surface of the substrate, is larger than a depth of the source region and a depth of the drain region, and a width of the first part of gate groove, measured along a horizontal direction, is less than a width of the second part of the gate groove; and   a gate conductive layer on the gate dielectric layer of the substrate and in the gate groove, the gate conductive layer extending from the first portion to the second portion of the gate dielectric layer so that the gate conductive layer has a region overlapping with the source region and the drain region respectively.   
     
     
         2 . The transistor according to  claim 1 , wherein the source region and the drain region are both adjacent to an opening part of the gate groove, and a side edge boundary of the source region and a side edge boundary of the drain region extend to sidewalls of the gate groove adjacent to the opening part,
 the gate dielectric layer covers a bottom and the sidewalls of the gate groove, and the second portion of the gate dielectric layer covers a part of the gate groove adjacent to the opening part so that the second portion covers parts of the source region and the drain region that extend to the sidewalls of the gate groove, and   the gate conductive layer fills the gate groove, and a part of the gate conductive layer adjacent to the opening part of the gate groove overlaps with the source region and the drain region.   
     
     
         3 . The transistor according to  claim 2 , wherein the source region and the drain region both extend from the top surface of the substrate towards an inner part of the substrate to a first depth, a top surface of the gate conductive layer is not higher than the top surface of the substrate and is located at a second depth of the substrate, and the first depth is greater than the second depth so that the source region and the drain region overlap with the gate conductive layer in a range from the first depth to the second depth respectively. 
     
     
         4 . The transistor according to  claim 2 , wherein a top of the gate conductive layer is lower than the opening part of the gate groove to form an accommodating space in the gate groove and above the gate conductive layer, and the transistor further comprises:
 an insulation layer filling the accommodating space of the gate groove to cover the gate conductive layer.   
     
     
         5 . The transistor according to  claim 1 , wherein the average thickness of the first portion of the gate dielectric layer is less than 3 nm, and the average thickness of the second portion of the gate dielectric layer is greater than or equal to 3 nm. 
     
     
         6 . The transistor according to  claim 1 , further comprising:
 an isolation layer on the substrate, the isolation layer covering the top surface of the substrate corresponds to the source region and the drain region.   
     
     
         7 . The transistor according to  claim 1 , further comprising:
 a well region in the substrate, and the source region and the drain region are both in the well region.   
     
     
         8 . The transistor according to  claim 1 , wherein the first portion of the gate dielectric layer has a thickness between a first thickness and a second thickness, the second portion of the gate dielectric layer has the second thickness, a part of the first portion that has the second thickness is located at a junction of the overlapping region and the channel region, and wherein, from the junction of the overlapping region and the channel region to a center of the channel region, the thickness of the first portion is reduced from the second thickness to the first thickness.