Sample well fabrication techniques and structures for integrated sensor devices

Abstract

Methods of forming an integrated device, and in particular forming one or more sample wells in an integrated device, are described. The methods may involve forming a metal stack over a cladding layer, forming an aperture in the metal stack, forming first spacer material within the aperture, and forming a sample well by removing some of the cladding layer to extend a depth of the aperture into the cladding layer. In the resulting sample well, at least one portion of the first spacer material is in contact with at least one layer of the metal stack.

What is claimed is: 
     
         1 . A method of forming an integrated device, the method comprising:
 forming a metal stack over a cladding layer;   forming an aperture in the metal stack;   forming first spacer material within the aperture; and   forming a sample well by removing some of the cladding layer to extend a depth of the aperture into the cladding layer, wherein at least one portion of the first spacer material is in contact with at least one layer of the metal stack.   
     
     
         2 . The method of  claim 1 , wherein forming the metal stack further comprises forming the metal stack on the cladding layer. 
     
     
         3 . The method of  claim 1 , wherein forming the first spacer material further comprises forming the first spacer material over the metal stack and at a bottom surface of the aperture. 
     
     
         4 . The method of  claim 1 , wherein forming the sample well further comprises performing a first directional etch to remove at least some of the first spacer material disposed on a top surface of the metal stack and on a bottom surface of the aperture. 
     
     
         5 . The method of  claim 1 , wherein the first spacer material includes at least one material configured to reduce formation of metal fluoride residue during an etch process used in forming the sample well. 
     
     
         6 . The method of  claim 1 , wherein the first spacer material includes at least one material configured to reduce formation of metal fluoride residue on at least one metal layer of the metal stack during an etch process used in forming the sample well. 
     
     
         7 . The method of  claim 1 , wherein the at least one portion of the first spacer material is disposed at an undercut region of the metal stack. 
     
     
         8 . The method of  claim 1 , wherein the metal stack comprises at least one aluminum containing layer and at least one titanium containing layer. 
     
     
         9 . The method of  claim 1 , wherein the first spacer material is formed by plasma enhanced chemical vapor deposition (PECVD). 
     
     
         10 . The method of  claim 1 , wherein the first spacer material includes at least one silicon material. 
     
     
         11 . The method of  claim 1 , wherein the first spacer material comprises one or more layers selected from the group of: amorphous silicon (a-Si), SiO2, SiON, SiN, and silicon alloy. 
     
     
         12 . The method of  claim 1 , wherein the first spacer material is formed by atomic layer deposition (ALD). 
     
     
         13 . The method of  claim 1 , wherein the first spacer material comprises one or more layers selected from the group of: TiO 2 , Al 2 O 3 , SiO 2 , HfO 2 , TiN, Ta 2 O 5 , and ZrO 2 . 
     
     
         14 . The method of  claim 1 , wherein the cladding layer comprises SiO2. 
     
     
         15 . The method of  claim 1 , further comprising:
 forming second spacer material into the sample well; and   removing at least some of the second spacer material at a bottom surface of the sample well to expose a portion of the cladding layer, wherein at least one portion of the second spacer material is in contact with one or more of the metal stack, the at least one portion of the first spacer material, and the cladding later.   
     
     
         16 . The method of  claim 15 , wherein forming the second spacer material further comprises forming the second spacer material over the metal stack. 
     
     
         17 . The method of  claim 15 , wherein removing the at least some of the second spacer material further comprises performing a directional etch to remove second spacer material disposed on a top surface of the metal stack and on the bottom surface of the sample well. 
     
     
         18 . The method of  claim 17 , wherein the directional etch comprises a fluorocarbon based etch. 
     
     
         19 . The method of  claim 15 , wherein the second spacer material is formed by atomic layer deposition (ALD). 
     
     
         20 . The method of  claim 19 , wherein the second spacer material comprises one or more layers selected from the group of: TiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , and Ta 2 O 5 . 
     
     
         21 . A method of forming an integrated device, the method comprising: forming a metal stack over a cladding layer;
 forming a dielectric layer over the metal stack;   forming an aperture in the metal stack by forming an opening in the dielectric layer and using the dielectric layer as a mask in removing a portion of the metal stack; and   forming a sample well by removing a portion of the cladding layer, wherein at least a portion of dielectric layer is removed while forming the sample well.   
     
     
         22 . The method of  claim 21 , wherein forming the metal stack further comprises forming the metal stack on the cladding layer. 
     
     
         23 . The method of  claim 21 , wherein forming the dielectric material further comprises forming the dielectric layer on the metal stack. 
     
     
         24 . The method of  claim 21 , wherein forming the aperture further comprises etching the opening in the dielectric layer and using the dielectric layer as an etch mask to form the aperture in the metal stack. 
     
     
         25 . The method of  claim 21 , wherein forming the sample well further comprises etching the cladding layer and the dielectric layer simultaneously. 
     
     
         26 . The method of  claim 21 , wherein the metal stack comprises at least one aluminum containing layer and at least one titanium containing layer. 
     
     
         27 . The method of  claim 21 , wherein the cladding layer comprises SiO2. 
     
     
         28 . The method of  claim 21 , further comprising:
 forming a spacer layer over the metal stack and into the sample well; and   performing a directional etch to remove portions of the spacer layer disposed on a top surface of the metal stack and on a bottom surface of the sample well to expose a portion of the cladding layer;   wherein at least one portion of the spacer layer forms at least one sidewall of the sample well.   
     
     
         29 . The method of  claim 28 , wherein the spacer layer is formed by atomic layer deposition (ALD). 
     
     
         30 . The method of  claim 28 , wherein the spacer layer comprises one or more layers selected from the group of: TiO 2 , Al 2 O 3 , HfO 2 , ZrO 2 , and Ta 2 O 5 . 
     
     
         31 . The method of  claim 21 , wherein forming the sample well further comprises substantially removing the dielectric layer. 
     
     
         32 . The method of  claim 21 , wherein the integrated device after forming the sample well does not include the dielectric layer. 
     
     
         33 . The method  claim 21 , wherein the dielectric layer comprises one or more selected from the group of: amorphous silicon (a-Si), SiO 2 , SiON, SiN, and silicon alloy. 
     
     
         34 - 42 . (canceled)