Power efficient multiply-accumulate circuitry

Abstract

Disclosed herein includes a system, a method, and a device for multiply-accumulate operation. In one aspect, an input operand is received by control circuitry. In one aspect, the control circuitry determines a sparsity of the input operand, where the sparsity may indicate whether a value of the input operand has a predetermined value or not. In one aspect, the control circuitry determines a stationarity of the input operand, where the stationarity may indicate whether the value of the input operand changes over one or more clock cycles. In one aspect, the input operand is provided to multiply-accumulate circuitry as an input, according to the determined sparsity and stationarity of the input operand.

What is claimed is: 
     
         1 . A device, comprising control circuitry configured to:
 receive an input operand;   determine a sparsity of the input operand, the sparsity indicating whether a value of the input operand has a predetermined value or not;   determine a stationarity of the input operand, the stationarity indicating whether the value of the input operand changes over one or more clock cycles; and   provide the input operand to multiply-accumulate (MAC) circuitry as an input, according to the determined sparsity and stationarity of the input operand.   
     
     
         2 . The device of  claim 1 , wherein the input operand includes at least one of a weight or an activation value of a neural network. 
     
     
         3 . The device of  claim 1 , wherein the control circuitry is configured to:
 in response to determining that the value of the input operand has the predetermined value, determine that the input operand is sparse, and   in response to determining that the value of the input operand does not have the predetermined value, determine that the input operand is not sparse.   
     
     
         4 . The device of  claim 1 , wherein the control circuitry is configured to:
 in response to determining that the value of the input operand remains unchanged over the one or more clock cycles, determine that the input operand is stationary, and   in response to determining that the value of the input operand changes within the one or more clock cycles, determine that the input operand is not stationary.   
     
     
         5 . The device of  claim 1 , further comprising holding circuitry, wherein
 the holding circuitry comprises:
 one or more operand registers coupled to one or more inputs of the MAC circuitry; and 
 an accumulation register coupled between an output port of the MAC circuitry and a feedback port of the MAC circuitry, and 
   the control circuitry is configured to generate one or more control signals according to the determined sparsity and stationarity of the input operand, and provide the one or more control signals to the holding circuitry.   
     
     
         6 . The device of  claim 5 , wherein the one or more control signals include at least one of a load signal or a bubble signal. 
     
     
         7 . The device of  claim 5 , wherein
 in response to at least one of (1) the input operand not being stationary or (2) the input operand not being sparse, the one or more operand registers are configured to provide the input operand to the one or more inputs of the MAC circuitry.   
     
     
         8 . The device of  claim 7 , wherein
 the input operand is provided to the one or more inputs of the MAC circuitry for a first clock cycle, and   the one or more operand registers are configured to:
 in response to (1) a next input operand for one or more clock cycles subsequent to the first clock cycle being stationary, and (2) the next input operand being sparse, hold the provided input operand at the one or more inputs of the MAC circuitry. 
   
     
     
         9 . The device of  claim 5 , wherein
 the control circuitry configured to receive a first input operand and a second input operand, and   the holding circuitry is configured to:
 in response to (1) the first input operand not being sparse and (2) the second input operand not being sparse, update accumulated data according to a summation output from the MAC circuitry and provide the updated accumulated data to the feedback port of the MAC circuitry. 
   
     
     
         10 . The device of  claim 9 , wherein the holding circuitry is configured to:
 in response to at least one of (1) the first input operand being sparse or (2) the second input operand being sparse, hold accumulated data in the accumulation register such that the MAC circuitry does not perform accumulation.   
     
     
         11 . A method comprising:
 receiving, by control circuitry, an input operand;   determining, by the control circuitry, a sparsity of the input operand, the sparsity indicating whether a value of the input operand has a predetermined value or not;   determining by the control circuitry, a stationarity of the input operand, the stationarity indicating whether the value of the input operand changes over one or more clock cycles; and   providing the input operand to multiply-accumulate (MAC) circuitry as an input, according to the determined sparsity and stationarity of the input operand.   
     
     
         12 . The method of  claim 11 , wherein the input operand includes at least one of a weight or an activation value of a neural network. 
     
     
         13 . The method of  claim 11 , further comprising:
 in response to determining that the value of the input operand has the predetermined value, determining that the input operand is sparse, and   in response to determining that the value of the input operand does not have the predetermined value, determining that the input operand is not sparse.   
     
     
         14 . The method of  claim 11 , further comprising:
 in response to determining that the value of the input operand remains unchanged over the one or more clock cycles, determining that the input operand is stationary, and   in response to determining that the value of the input operand changes within the one or more clock cycles, determining that the input operand is not stationary.   
     
     
         15 . The method of  claim 11 , further comprising:
 generating, by the control circuitry, one or more control signals according to the determined sparsity and stationarity of the input operand; and   providing the one or more control signals to the holding circuitry.   
     
     
         16 . The method of  claim 15 , wherein the one or more control signals include at least one of a load signal or a bubble signal. 
     
     
         17 . The method of  claim 15 , further comprising:
 in response to at least one of (1) the input operand not being stationary or (2) the input operand not being sparse, providing, by one or more operand registers of the holding circuitry, the input operand to one or more inputs of the MAC circuitry.   
     
     
         18 . The method of  claim 17 , wherein
 the input operand is provided to the one or more inputs of the MAC circuitry for a first clock cycle, and   the method further comprises:
 in response to (1) a next input operand for one or more clock cycles subsequent to the first clock cycle being stationary, and (2) the next input operand being sparse, holding the provided input operand at the one or more inputs of the MAC circuitry. 
   
     
     
         19 . The method of  claim 15 , further comprising:
 receiving, by the control circuitry, a first input operand and a second input operand; and   in response to (1) the first input operand not being sparse and (2) the second input operand not being sparse, updating, by the holding circuitry, accumulated data according to a summation output from the MAC circuitry and providing the updated accumulated data to a feedback port of the MAC circuitry.   
     
     
         20 . The method of  claim 19 , further comprising:
 in response to at least one of (1) the first input operand being sparse or (2) the second input operand being sparse, holding accumulated data in an accumulation register coupled between an output port of the MAC circuitry and the feedback port of the MAC circuitry such that the MAC circuitry does not perform accumulation.