Apparatus and method for vector horizontal add of signed/unsigned words and doublewords

Abstract

An apparatus and method for performing a packed horizontal addition of words and doublewords. One embodiment of a processor includes a decoder to decode a packed horizontal add instruction which includes an opcode and one or more operands used to identify a plurality of packed words; a source register to store a plurality of packed words; execution circuitry to execute the decoded instruction, and a destination register to store a final result as a packed result word in a designated data element position. The execution circuitry includes operand selection circuitry to identify first and second packed words from the source register in accordance with the operands and opcode; adder circuitry to add the two packed words to generate a temporary sum; a temporary storage of at least 17 bits to store the temporary sum; and saturation circuitry to saturate the temporary sum if necessary to generate the final result.

What is claimed is: 
     
         1 . A processor comprising:
 decoder circuitry to decode an instruction, the instruction to identify a source register; and   execution circuitry to execute the decoded instruction to perform an addition of a first operand and a second operand to generate a temporary result, wherein the first and second operands are selected from respective first and second fixed positions of the source register,   the execution circuitry further to perform saturation of the temporary result to generate a final result, and to store the final result in a fixed position of a destination register.   
     
     
         2 . The processor of  claim 1 , wherein the instruction is further to identify the destination register. 
     
     
         3 . The processor of  claim 1 , wherein all bits of destination register, other than those storing the final result, are set to zero. 
     
     
         4 . The processor of  claim 1 , wherein the addition of the first and second operands comprises an unsigned addition. 
     
     
         5 . The processor of  claim 4 , wherein the first and second operands each comprises an unsigned word. 
     
     
         6 . The processor of  claim 5 , wherein the final result comprises an unsigned word. 
     
     
         7 . The processor of  claim 6 , wherein the source register comprises a 128-bit register, the first fixed position comprises bits [15:0] of the source register and the second fixed position comprises bits [79:64] of the source register. 
     
     
         8 . The processor of  claim 6 , wherein the final result is stored to a first word element position of the destination register. 
     
     
         9 . The processor of  claim 8 , wherein the first word element position comprises bits [15:0] of the destination register. 
     
     
         10 . The processor of  claim 4 , wherein the first and second operands each comprises an unsigned doubleword. 
     
     
         11 . The processor of  claim 10 , wherein the final result comprises an unsigned doubleword. 
     
     
         12 . The processor of  claim 11 , wherein the source register comprises a 128-bit register, the first fixed position comprises bits [31:0] of the source register and the second fixed position comprises bits [95:64] of the source register. 
     
     
         13 . The processor of  claim 11 , wherein the final result is stored to a first doubleword element position of the destination register. 
     
     
         14 . The processor of  claim 13 , wherein the first doubleword element position comprises bits [31:0] of the destination register. 
     
     
         15 . The processor of  claim 1 , wherein the addition of the first and second operands comprises a signed addition. 
     
     
         16 . The processor of  claim 15 , wherein the first and second operands each comprises a signed word. 
     
     
         17 . The processor of  claim 16 , wherein the final result comprises a signed word. 
     
     
         18 . The processor of  claim 17 , wherein the source register comprises a 128-bit register, the first fixed position comprises bits [15:0] of the source register and the second fixed position comprises bits [79:64] of the source register. 
     
     
         19 . The processor of  claim 17 , wherein the final result is stored to a first word element position of the destination register. 
     
     
         20 . The processor of  claim 19 , wherein the first word element position comprises bits [15:0] of the destination register. 
     
     
         21 . The processor of  claim 15 , wherein the first and second operands each comprises a signed doubleword. 
     
     
         22 . The processor of  claim 21 , wherein the final result comprises a signed doubleword. 
     
     
         23 . The processor of  claim 22 , wherein the source register comprises a 128-bit register, the first fixed position comprises bits [31:0] of the source register and the second fixed position comprises bits [95:64] of the source register. 
     
     
         24 . The processor of  claim 22 , wherein the final result is stored to a first doubleword element position of the destination register. 
     
     
         25 . The processor of  claim 24 , wherein the first doubleword element position comprises bits [31:0] of the destination register.