Anti-ferroelectric capacitor memory cell

Abstract

Described herein are anti-ferroelectric (AFE) memory cells and corresponding methods and devices. For example, in some embodiments, an AFE memory cell disclosed herein includes a capacitor employing an AFE material between two capacitor electrodes. Applying a voltage to one electrode of such capacitor allows boosting the charge at the other electrode, where nonlinear behavior of the AFE material between the two electrodes may advantageously manifest itself in that, for a given voltage applied to the first electrode, a factor by which the charge is boosted at the second electrode of the capacitor may be substantially different for different values of charge at that electrode before the boost. Connecting the second capacitor electrode to a storage node of the memory cell may then allow boosting the charge on the storage node so that different logic states of the memory cell become more clearly resolvable, enabling increased retention times.

1 . An integrated circuit (IC) device, comprising:
 a storage node;   a first transistor, coupled to the storage node;   a second transistor, coupled to the storage node; and   a capacitor, coupled to the storage node, the capacitor comprising a first capacitor electrode, a second capacitor electrode, and a material between the first and second capacitor electrodes,   wherein the material includes hafnium and oxygen doped with one or more of silicon, aluminum, yttrium, gadolinium, germanium, lead, zirconium, titanium, tin, strontium, lanthanum, and niobium.   
     
     
         2 . The IC device according to  claim 1 , wherein a gate terminal of the first transistor is coupled to a write wordline. 
     
     
         3 . The IC device according to  claim 1 , wherein one of a source terminal and a drain terminal of the first transistor is coupled to the storage node. 
     
     
         4 . The IC device according to  claim 3 , wherein another one of the source terminal and the drain terminal of the first transistor is coupled to a write bitline. 
     
     
         5 . The IC device according to  claim 1 , wherein a gate terminal of the second transistor is coupled to the storage node. 
     
     
         6 . The IC device according to  claim 1 , wherein one of a source terminal and a drain terminal of the second transistor is coupled to a read bitline. 
     
     
         7 . The IC device according to  claim 6 , wherein another one of the source terminal and the drain terminal of the second transistor is coupled to a supply voltage or ground. 
     
     
         8 . The IC device according to  claim 1 , wherein the first capacitor electrode is coupled to a plate-line. 
     
     
         9 . The IC device according to  claim 1 , wherein the second capacitor electrode is coupled to the storage node. 
     
     
         10 . The IC device according to  claim 9 , wherein a gate terminal of the second transistor is coupled to the second capacitor electrode via the storage node. 
     
     
         11 . The IC device according to  claim 1 , wherein at least one of the first transistor and the second transistor is a transistor in which a channel region of the transistor is a portion of a fin and a gate stack of the non-planar transistor at least partially wraps around a part of the fin. 
     
     
         12 . The IC device according to  claim 1 , wherein at least one of the first transistor and the second transistor is a transistor in which a channel region of the transistor is a portion of a nanoribbon or a nanowire and a gate stack of the non-planar transistor at least partially wraps around a part of the nanoribbon or the nanowire. 
     
     
         13 . The IC device according to  claim 1 , wherein the material has a thickness between 0.5 and 15 nanometers. 
     
     
         14 . A method of manufacturing an integrated circuit (IC) device, the method comprising:
 providing a storage node;   providing a first transistor, coupled to the storage node;   providing a second transistor, coupled to the storage node; and   providing a capacitor, coupled to the storage node, the capacitor comprising a first capacitor electrode, a second capacitor electrode, and a material between the first and second capacitor electrodes,   wherein the material includes hafnium and oxygen doped with one or more of silicon, aluminum, yttrium, gadolinium, germanium, lead, zirconium, titanium, tin, strontium, lanthanum, and niobium.   
     
     
         15 . The method according to  claim 14 , wherein:
 a gate terminal of the first transistor is coupled to a first control line,   one of a source terminal and a drain terminal of the first transistor is coupled to the storage node, and   another one of the source terminal and the drain terminal of the first transistor is coupled to a second control line.   
     
     
         16 . The method according to  claim 14 , wherein:
 a gate terminal of the second transistor is coupled to the storage node,   one of a source terminal and a drain terminal of the second transistor is coupled to a control line, and   another one of the source terminal and the drain terminal of the second transistor is coupled to a supply voltage or ground.   
     
     
         17 . An apparatus, comprising:
 an integrated circuit (IC) die; and   a further IC element coupled to the IC die,   wherein the IC die includes a memory device that includes a plurality of memory cells, wherein an individual memory cell of the plurality of memory cells includes:
 a storage node, and 
 a capacitor, coupled to the storage node, the capacitor comprising a first capacitor electrode, a second capacitor electrode, and a capacitor insulator between the first and second capacitor electrodes, 
 wherein the capacitor insulator includes hafnium and oxygen doped with one or more of silicon, aluminum, yttrium, gadolinium, germanium, lead, zirconium, titanium, tin, strontium, lanthanum, or niobium. 
   
     
     
         18 . The apparatus according to  claim 17 , wherein the further IC element is one of an interposer, a circuit board, a flexible board, or a package substrate. 
     
     
         19 . The apparatus according to  claim 17 , wherein the apparatus is a wearable or handheld device. 
     
     
         20 . The apparatus according to  claim 17 , wherein the apparatus further includes one or more communication chips and an antenna.