US2022230906A1PendingUtilityA1
3d semiconductor device and structure with nand logic
Est. expiryNov 18, 2030(~4.3 yrs left)· nominal 20-yr term from priority
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Claims
Abstract
A 3D semiconductor device including: a first level including a single crystal layer and plurality of first transistors; a first metal layer including interconnects between first transistors, where the interconnects between the first transistors includes forming logic gates; a second metal layer atop at least a portion of the first metal layer, second transistors which are vertically oriented, are also atop a portion of the second metal layer; where at least eight of the first transistors are connected in series forming at least a portion of a NAND logic structure, where at least one of the second transistors is at least partially directly atop of the NAND logic structure; and a third metal layer atop at least a portion of the second transistors, where the second metal layer is aligned to the first metal layer with a less than 150 nm misalignment.
Claims
exact text as granted — not AI-modifiedWe claim:
1 . A 3D semiconductor device, the device comprising:
a first level comprising a single-crystal layer and a plurality of first transistors; a first metal layer comprising interconnects between said plurality of first transistors,
wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates;
a second metal layer atop at least a portion of said first metal layer, a plurality of second transistors atop at least a portion of said second metal layer,
wherein at least eight of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure,
wherein said plurality of second transistors are vertically oriented transistors, and
wherein at least one of said second transistors is at least partially directly atop of said NAND logic structure; and
a third metal layer atop at least a portion of said plurality of second transistors, and a connecting conductive line between an output of said at least a portion of a NAND logic structure to at least one of said second transistors,
wherein said second metal layer is aligned to said first metal layer with less than 150 nm misalignment.
2 . The 3D semiconductor device according to claim 1 ,
wherein at least one of said plurality of second transistors comprises a gate all around structure.
3 . The 3D semiconductor device according to claim 1 , further comprising:
a TSV,
wherein said TSV is disposed through said single crystal layer to provide connection to an external device.
4 . The 3D semiconductor device according to claim 1 ,
wherein at least one of said second transistors comprises a source, a channel and a drain having similar doping.
5 . The 3D semiconductor device according to claim 1 ,
wherein said vertically oriented transistor is defined by having a majority of on-current through said vertically oriented transistor channel is oriented perpendicularly with respect to an orientation of said first level.
6 . The 3D semiconductor device according to claim 1 ,
wherein at least six of said plurality of second transistors are connected in series.
7 . The 3D semiconductor device according to claim 1 , further comprising:
a fourth metal layer atop at least a portion of said second metal layer,
wherein said second metal layer thickness is greater than said fourth metal thickness by at least 50%.
8 . A 3D semiconductor device, the device comprising:
a first level comprising a single-crystal layer and a plurality of first transistors; a first metal layer comprising interconnects between said plurality of first transistors,
wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates;
a second metal layer disposed atop at least a portion of said first metal layer, a plurality of second transistors disposed atop at least a portion of said second metal layer,
wherein at least eight of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure,
wherein said plurality of second transistors are vertically oriented transistors, and
wherein at least one of said second transistors is at least partially directly atop of said NAND logic structure;
a third metal layer disposed atop at least a portion of said plurality of second transistors, and a connecting conductive line between an output of said at least a portion of a NAND logic structure to at least one of said second transistors,
wherein said second metal layer is aligned to said first metal layer with less than 150 nm misalignment, and
wherein at least one of said second transistors comprises a metal gate.
9 . The 3D semiconductor device according to claim 8 ,
wherein at least one of said plurality of second transistors comprises a gate all around structure.
10 . The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors comprises a metal gate formed using a gate replacement process.
11 . The 3D semiconductor device according to claim 8 ,
wherein at least one of said second transistors comprises a source, a channel and a drain having a same doping type.
12 . The 3D semiconductor device according to claim 8 ,
wherein said vertically oriented transistor is defined by having a majority of on-current through a channel of said vertically oriented transistor oriented perpendicularly with respect to an orientation of said first level.
13 . The 3D semiconductor device according to claim 8 ,
wherein at least six of said plurality of second transistors are connected in series.
14 . The 3D semiconductor device according to claim 8 , further comprising:
a fourth metal layer disposed atop at least a portion of said second metal layer,
wherein said second metal layer thickness is greater by at least 50% than said fourth metal thickness.
15 . A 3D semiconductor device, the device comprising:
a first level comprising a single-crystal layer and a plurality of first transistors; a first metal layer comprising interconnects between said plurality of first transistors,
wherein said interconnects between said plurality of first transistors comprises forming a plurality of logic gates;
a second metal layer disposed atop at least a portion of said first metal layer; a plurality of second transistors disposed atop at least a portion of said second metal layer,
wherein at least eight of said plurality of first transistors are connected in series forming at least a portion of a NAND logic structure,
wherein said plurality of second transistors are vertically oriented transistors, and
wherein at least one of said second transistors is at least partially directly atop of said NAND logic structure;
a third metal layer disposed atop at least a portion of said plurality of second transistors, and a connecting conductive line between an output of said at least a portion of a NAND logic structure to at least one of said second transistors,
wherein said second metal layer is aligned to said first metal layer with less than 150 nm misalignment, and
wherein a distance from at least one of said second transistors and at least a portion of said second metal is less than 2 microns.
16 . The 3D semiconductor device according to claim 15 ,
wherein at least one of said plurality of second transistors comprises a gate all around structure.
17 . The 3D semiconductor device according to claim 15 ,
wherein at least one of said second transistors comprises a metal gate.
18 . The 3D semiconductor device according to claim 15 ,
wherein at least one of said second transistors comprises a source, a channel and a drain having a same doping type.
19 . The 3D semiconductor device according to claim 15 ,
wherein at least six of said plurality of second transistors are connected in series.
20 . The 3D semiconductor device according to claim 15 , further comprising:
a fourth metal layer disposed atop at least a portion of said second metal layer,
wherein said second metal layer thickness is greater by at least 50% than said fourth metal thickness.Join the waitlist — get patent alerts
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