Performance modeling of graph processing computing architectures

Abstract

A distributed simulation system is provided that includes a timing simulator and functional simulator(s) on different computing nodes to simulate a graph processing system. The functional simulators are to simulate execution of a set of instructions on the graph processing system and to send information associated with the simulated set of instructions to the timing simulator over the network. The timing simulator is to determine timing information associated with execution of the sets of instructions sent by the functional simulators and send the timing information to the functional simulators over the network. The timing simulator may determine a global synchronization point for the functional simulators and send the timing information for the sets of instructions to respective functional simulators at the global synchronization point. The functional simulators may stall simulation of further instructions until the timing information for its set of instructions is received from the timing simulator.

What is claimed is: 
     
         1 . A distributed simulation system comprising:
 a first computing node to execute a timing simulator of a graph processing system; and   one or more second computing nodes coupled to the first computing node over a network, the second computing nodes to execute functional simulators of a graph processing system;   wherein:
 the functional simulators are to simulate execution of instructions on the graph processing system and send information associated with the simulated instructions to the timing simulator over the network; and 
 the timing simulator is to determine timing information associated with execution of the instructions sent by the functional simulators, and send the timing information to the functional simulators over the network. 
   
     
     
         2 . The system of  claim 1 , wherein at least one functional simulator is to execute a simulation of a component of the graph processing system, and to send instruction information to the timing simulator after a predetermined number of instructions have been simulated by the functional simulator for the component. 
     
     
         3 . The system of  claim 2 , wherein the component is a single threaded core of the graph processing system. 
     
     
         4 . The system of  claim 2 , wherein the component is a multi-threaded core of the graph processing system, and the functional simulator is to send instruction information to the timing simulator after a predetermined number of instructions have been simulated by functional simulator for all of the threads of the multi-threaded core in aggregate. 
     
     
         5 . The system of  claim 4 , wherein the timing simulator is to determine a thread interleaving factor for the multi-threaded core and send the interleaving factor to the functional simulator, the thread interleaving factor indicating a quantity of instructions to simulate for each thread of the multi-threaded core per cycle. 
     
     
         6 . The system of  claim 2 , wherein the component is an accelerator of the graph processing system, and the functional simulator is to send instruction information to the timing simulator after a predetermined quantity of sub-instructions of an accelerator instruction have been executed. 
     
     
         7 . The system of  claim 2 , wherein the functional simulator is to send the instruction information to the timing simulator, without waiting for the predetermined quantity of instructions to be simulated, based on one or more of a wait-for-DMA instruction, an atomic operation, an enqueue/dequeue operation, and a memory scatter instruction being simulated on the functional simulator. 
     
     
         8 . The system of  claim 1 , wherein the timing information for respective sets of instructions includes a quantity of cycles required to execute the set of instructions on the graph processing system. 
     
     
         9 . The system of  claim 1 , wherein:
 the timing simulator is to determine a global synchronization point for a plurality of functional simulators, and send the timing information for the sets of instructions to the respective functional simulators at the global synchronization point; and   the functional simulator are to stall simulation of further instructions until the timing information for the its set of instructions is received from the timing simulator.   
     
     
         10 . The system of  claim 9 , wherein the timing simulator is to maintain a local timestamp for each thread being simulated on a functional simulator and a global timestamp, and to determine the global synchronization point based on comparisons between the local timestamps and the global timestamp. 
     
     
         11 . The system of  claim 1 , wherein the instruction information includes instruction opcodes and data addresses associated with the opcodes. 
     
     
         12 . The system of  claim 11 , wherein the instruction information further includes data values. 
     
     
         13 . The system of  claim 1 , wherein the instruction information includes the instructions. 
     
     
         14 . The system of  claim 1 , wherein the second computing nodes are to communicate with one another via a Message Passing Interface (MPI). 
     
     
         15 . The system of  claim 1 , wherein the first computing node does not execute a functional simulator and the second computing nodes do not execute timing simulators. 
     
     
         16 . The system of  claim 1 , wherein the network is an Ethernet-based network or Infiniband-based network. 
     
     
         17 . A method comprising:
 at a plurality of functional simulators, simulating execution of instructions on components of a graph processing system and sending information associated with the simulated instructions to a timing simulator; and   at a timing simulator, determining timing information associated with execution of the instructions sent by the functional simulators and sending the timing information to the functional simulators.   
     
     
         18 . The method of  claim 17 , further comprising:
 determining, by the timing simulator, a global synchronization point for the functional simulators, and send the timing information for the sets of instructions to respective functional simulators at the global synchronization point; and   at the functional simulators, stalling simulation of further instructions until the timing information is received from the timing simulator.   
     
     
         19 . The method of  claim 17 , further comprising maintaining, by the timing simulator, a local timestamp for each thread being simulated on a functional simulator and a global timestamp, wherein the global synchronization point is determined based on comparisons between the local timestamps and the global timestamp. 
     
     
         20 . One or more non-transitory computer-readable media comprising instructions that, when executed by processors of a distributed simulation system, cause the processors to:
 receive, from a plurality of functional simulators, information associated with the simulated execution of instructions on components of a graph processing system;   determine timing information associated with execution of the instructions sent by the functional simulators;   determine a global synchronization point for the functional simulators; and   send the timing information for the sets of instructions to respective functional simulators at the global synchronization point.   
     
     
         21 . The computer-readable media of  claim 20 , wherein the instructions are further to determine a thread interleaving factor for a multi-threaded core being simulated by a functional simulator and send the interleaving factor to the functional simulator, the thread interleaving factor indicating a quantity of instructions to simulate for each thread of the multi-threaded core per cycle. 
     
     
         22 . The computer-readable media of  claim 20 , wherein the instructions are to maintain a local timestamp for each thread being simulated on a functional simulator and a global timestamp, and wherein the global synchronization point is determined based on comparisons between the local timestamps and the global timestamp. 
     
     
         23 . One or more non-transitory computer-readable media comprising instructions that, when executed by processors of a distributed simulation system, cause the processors to:
 simulate execution of instructions on a component of a graph processing system;   after a predetermined quantity of instructions have been simulated for the component, cause information associated with the simulated instructions to be sent to a timing simulator over a network; and   stall simulation of further instructions until timing information is received from the timing simulator for the quantity of instructions.   
     
     
         24 . The computer-readable media of  claim 23 , wherein simulating execution of instructions comprises simulating a multi-threaded core of the graph processing system, and the instructions are further to send the instruction information to the timing simulator after a predetermined quantity of instructions have been simulated all of the threads the multi-threaded core in aggregate. 
     
     
         25 . The computer-readable media of  claim 23 , wherein the instruction information includes instruction opcodes and data addresses associated with the opcodes.