Field effect transistor (fet) stack and methods to form same

Abstract

The disclosure provides a field effect transistor (FET) stack with methods to form the same. The FET stack includes a first transistor over a substrate. The first transistor includes a first active semiconductor material including a first channel region between a first set of source/drain terminals, and a first gate structure over the first channel region. The first gate structure includes a first gate insulator of a first thickness above the first channel region. A second transistor is over the substrate and horizontally separated from the first transistor. A second gate structure of the second transistor may include a second gate insulator of a second thickness above a second channel region, the second thickness being greater than the first thickness. A shared gate node may be coupled to each of the first gate structure and the second gate structure.

What is claimed is: 
     
         1 . A field effect transistor (FET) stack, comprising:
 a first transistor over a substrate, including:
 a first active semiconductor material having a first conductive dopant concentration and including a first channel region between a first set of source/drain terminals, and 
 a first gate structure over the first channel region; 
   a second transistor over the substrate and horizontally separated from the first transistor, the second transistor including:
 a second active semiconductor material having a second conductive dopant concentration and including a second channel region between a second set of source/drain terminals, wherein the second conductive dopant concentration is greater than the first conductive dopant concentration, and a selected one of the set of second source/drain terminals is coupled to a selected one of the first set of source/drain terminals of the first transistor; and 
 a second gate structure over the second channel region; and 
   a shared gate node coupled to each of the first gate structure and the second gate structure.   
     
     
         2 . The FET stack of  claim 1 , further comprising a third transistor over the substrate and horizontally between the first transistor and the second transistor, the third transistor including:
 a third active semiconductor material including a third channel region between a third set of source/drain terminals having a third conductive dopant concentration greater than the first conductive dopant concentration and less than the second conductive dopant concentration, wherein the selected one of the first set of source/drain terminals is coupled to the selected one of the second set of source/drain terminals through the third set of source/drain terminals; and   a third gate structure over the third channel region.   
     
     
         3 . The FET stack of  claim 2 , wherein a difference between the first conductive dopant concentration and the second conductive dopant concentration is approximately equal to a difference between the second conductive dopant concentration and the third conductive dopant concentration. 
     
     
         4 . The FET stack of  claim 1 , wherein a gate length of the first gate structure is approximately equal to a gate length of the second gate structure. 
     
     
         5 . The FET stack of  claim 1 , further comprising:
 at least one trench isolation on the substrate between the first active semiconductor material and the second active semiconductor material; and   a buried insulator layer directly beneath each of the first active semiconductor material and the second active semiconductor material.   
     
     
         6 . The FET stack of  claim 1 , wherein a difference between the second conductive dopant concentration and the first conductive dopant concentration causes a threshold voltage of the second transistor to be greater than a threshold voltage of the first transistor. 
     
     
         7 . The FET stack of  claim 1 , wherein the first conductive dopant and the second conductive dopant includes one of boron (B) or arsenic (As). 
     
     
         8 . The FET stack of  claim 1 , wherein the FET stack comprises one of a series FET stack or a shunt FET stack within an radio frequency (RF) switching circuit. 
     
     
         9 . A method to form a field effect transistor (FET) stack for an integrated circuit, the method comprising:
 forming a first semiconductor well and a second semiconductor well over a substrate, wherein the first semiconductor well is horizontally separated from the second semiconductor well;   introducing a dopant within the first semiconductor well and the second semiconductor well to yield a first active semiconductor material and a second active semiconductor material, such that the first active semiconductor material has a first dopant concentration that is different from a second dopant concentration of the second semiconductor well;   electrically coupling a first source/drain terminal of the first active semiconductor material to a second source/drain terminal of the second active semiconductor material;   forming a plurality of gate structures including a first gate structure on a first channel region of the first active semiconductor material and a second gate structure on a second channel region of the second active semiconductor material, wherein a threshold voltage of the second gate structure over the second active semiconductor material is greater than a threshold voltage of the first gate structure over the first active semiconductor material; and   electrically coupling each of the first gate structure and the second gate structure to a shared gate node.   
     
     
         10 . The method of  claim 9 , wherein the dopant includes nitrogen (N), and forming the plurality of gate structures includes simultaneously forming a first gate insulator on the first active semiconductor material and a second gate insulator on the second active semiconductor material, such that the first gate insulator has a first thickness that is less than a second thickness of the second gate insulator. 
     
     
         11 . The method of  claim 9 , wherein the dopant includes a conductive dopant, and introducing the dopant causes the second active semiconductor material to have a higher concentration of the conductive dopant than the first active semiconductor material. 
     
     
         12 . The method of  claim 9 , wherein forming the plurality of gate structures includes forming the first gate structure with a gate length approximately equal to a gate length of the second gate structure. 
     
     
         13 . The method of  claim 9 , further comprising:
 forming at least one trench isolation on the substrate between the first active semiconductor material and the second active semiconductor material; and   forming a buried insulator layer directly beneath each of the first active semiconductor material and the second active semiconductor material.   
     
     
         14 . The method of  claim 9 , wherein the dopant includes one of boron (B) or arsenic (As). 
     
     
         15 . A method for forming a field effect transistor (FET) stack, comprising:
 forming a first transistor over a substrate, including:
 forming a first active semiconductor material having a first conductive dopant concentration and including a first channel region between a first set of source/drain terminals, and 
 forming a first gate structure over the first channel region; 
   forming a second transistor over the substrate and horizontally separated from the first transistor, including:
 forming a second active semiconductor material having a second conductive dopant concentration and including a second channel region between a second set of source/drain terminals, wherein the second conductive dopant concentration is greater than the first conductive dopant concentration; 
 coupling a selected one of the set of second source/drain terminals to a selected one of the first set of source/drain terminals of the first transistor; and 
 forming a second gate structure over the second channel region; and 
   coupling a shared gate node to each of the first gate structure and the second gate structure.   
     
     
         16 . The method of  claim 15 , further comprising:
 forming a third transistor over the substrate and horizontally between the first transistor and the second transistor, including:
 forming a third active semiconductor material including a third channel region between a third set of source/drain terminals having a third conductive dopant concentration greater than the first conductive dopant concentration and less than the second conductive dopant concentration; 
 coupling the selected one of the first set of source/drain terminals to the selected one of the second set of source/drain terminals through the third set of source/drain terminals; and 
 forming a third gate structure over the third channel region. 
   
     
     
         17 . The method of  claim 15 , wherein a difference between the first conductive dopant concentration and the second conductive dopant concentration is approximately equal to a difference between the second conductive dopant concentration and the third conductive dopant concentration. 
     
     
         18 . The method of  claim 15 , further comprising:
 forming at least one trench isolation on the substrate between the first active semiconductor material and the second active semiconductor material; and   forming a buried insulator layer directly beneath each of the first active semiconductor material and the second active semiconductor material.   
     
     
         19 . The method of  claim 15 , wherein a gate length of the first gate structure is approximately equal to a gate length of the second gate structure. 
     
     
         20 . The method of  claim 15 , wherein a difference between the second conductive dopant concentration and the first conductive dopant concentration causes a threshold voltage of the second transistor to be greater than a threshold voltage of the first transistor.