Memory integrity performance enhancement systems and methods

Abstract

A write request causes controller circuitry to write an encrypted data line and First Tier metadata portion including MAC data and a first portion of ECC data to a first memory circuitry portion and a second portion of ECC data to a sequestered, second memory circuitry portion. A read request causes the controller circuitry to read the encrypted data line and the First Tier metadata portion from the first memory circuitry portion. Using the first portion of the ECC data included in the First Tier metadata portion, the controller circuitry determines if an error exists in the encrypted data line. If no error is detected, the controller circuitry decrypts and verifies the data line using the MAC data included in the First Tier metadata portion. If an error in the data line is detected by the controller circuitry, the Second Tier metadata portion, containing the second portion of the ECC data is fetched from the sequestered, second memory circuitry portion and the error corrected.

What is claimed: 
     
         1 . A system, comprising:
 memory circuitry including a first memory circuitry portion and a second memory circuitry portion sequestered from the first memory circuitry portion; and   controller circuitry to:
 responsive to receipt of a read request generated by an application executed by processor circuitry to read a first data line of a plurality of data lines stored in the first memory circuitry portion, retrieve the first data line and first metadata associated with the first data line from the first memory circuitry portion, wherein the first metadata is to include an error detection data portion of an error correction code (ECC) associated with first data line; 
 determine, based on the error detection data portion of the ECC, whether an error exists in the first data line; 
 responsive to a determination that the first data line contains a first error, retrieve from the second memory circuitry portion, second metadata associated with the first data line and including at least a part of an error correction data portion of the ECC; 
 generate a corrected first data line by correcting at least the first error in the first data line based on the error correction data portion of the ECC; and 
 generate a decrypted first data line by decrypting the corrected first data line. 
   
     
     
         2 . The system of  claim 1 , wherein the controller circuitry is to further:
 verify the corrected first data line based on a message authentication code (MAC) associated with the first data line and included in the first metadata.   
     
     
         3 . The system of  claim 2 , wherein the controller circuitry is to further:
 responsive to an unsuccessful verification of the corrected first data line, generate a security exception.   
     
     
         4 . The system of  claim 2 , wherein the controller circuitry is to further:
 responsive to a successful verification of the corrected first data line, transfer the decrypted first data line to the processor circuitry.   
     
     
         5 . The system of  claim 2 , wherein decrypting the corrected first data line and verifying the corrected first data line are to be performed simultaneously or sequentially. 
     
     
         6 . The system of  claim 1 , wherein the first metadata further includes a second part of the error correction data portion of the ECC. 
     
     
         7 . The system of  claim 1 , wherein the first metadata is proximate to the first data line in the first memory circuitry portion of the memory circuitry. 
     
     
         8 . The system of  claim 1 , further comprising:
 memory controller circuitry communicatively coupled to the controller circuitry and to the memory circuitry, wherein to retrieve the first data line and the first metadata, the controller circuitry is to:
 forward the read request to the memory controller circuitry; and 
 receive the first data line and the first metadata from the memory controller circuitry. 
   
     
     
         9 . A method, comprising:
 receiving, by controller circuitry, a read request generated by an application executed by processor circuitry to read a first data line of a plurality of data lines stored in a first memory circuitry portion of memory circuitry;   responsive to receiving the read request, retrieving the first data line and first metadata associated with the first data line from the first memory circuitry portion, wherein the first metadata includes an error detection data portion of an error correction code (ECC) associated with first data line;   determining, based on the error detection data portion of the ECC, whether the first data line contains an error;   responsive to the determining that the first data line contains a first error, retrieving from a second memory circuitry portion sequestered from the first memory circuitry portion in the memory circuitry, second metadata associated with the first data line, the second metadata including at least a part of an error correction data portion of the ECC;   generating a corrected first data line by correcting at least the first error in the first data line based on the error correction data portion of the ECC; and   generating a decrypted first data line by decrypting the corrected first data line.   
     
     
         10 . The method of  claim 9 , further comprising:
 verifying the first data line based on a message authentication code (MAC) associated with the first data line and included in the first metadata.   
     
     
         11 . The method of  claim 9 , wherein the first metadata further includes a second part of the error correction data portion of the ECC. 
     
     
         12 . The method of  claim 9 , wherein the retrieving the first data line and the first metadata from the first memory circuitry portion further comprises:
 forwarding, from the controller circuitry, the read request to memory controller circuitry communicatively coupled to the memory circuitry; and   receiving, by the controller circuitry, the first data line and the first metadata from the memory controller circuitry.   
     
     
         13 . A non-transitory machine-readable medium including instructions that when executed by controller circuitry, cause the controller circuitry to:
 receive a read request generated by an application executed by processor circuitry to read a first data line of a plurality of data lines stored in a first memory circuitry portion of memory circuitry;   responsive to receiving the read request, retrieve the first data line and first metadata associated with the first data line from the first memory circuitry portion, wherein the first metadata is to include an error detection data portion of a first error correction code (ECC) associated with the first data line, and wherein second metadata associated with the first data line is to include at least a part of an error correction data portion of the first ECC and is to be stored in a second memory circuitry portion sequestered from the first memory circuitry portion in the memory circuitry;   determine, based on the error detection data portion of the first ECC associated with the first data line, whether the first data line contains an error; and   subsequent to a determination that the first data line contains no errors, generate a decrypted first data line by decrypting the first data line retrieved from the first memory circuitry portion.   
     
     
         14 . The non-transitory machine-readable medium of  claim 13 , wherein the instructions, when executed by the controller circuitry, cause the controller circuitry to further:
 responsive to the determination that the first data line contains no errors, refrain from retrieving the second metadata from the second memory circuitry portion.   
     
     
         15 . The non-transitory machine-readable medium of  claim 13 , wherein the instructions, when executed by the controller circuitry, cause the controller circuitry to further:
 subsequent to the determination that the first data line contains no errors, verify the first data line based on a message authentication code (MAC) associated with the first data line and included in the first metadata.   
     
     
         16 . The non-transitory machine-readable medium of  claim 13 , wherein the instructions, when executed by the controller circuitry, cause the controller circuitry to further:
 responsive to receipt of a second read request to read a second data line of the plurality of data lines, retrieve the second data line and third metadata associated with the second data line from the first memory circuitry portion, wherein the third metadata is to include a second error detection data portion of a second ECC associated with the second data line;   determine whether the second data line contains an error based on the second error detection data portion included in the third metadata;   responsive to a second determination that the second data line contains a first error, retrieve from the second memory circuitry portion, fourth metadata associated with the second data line and including at least a part of a second error correction data portion of the second ECC; and   generate a corrected second data line by correcting at least the first error in the second data line based on the second error correction data portion of the second ECC.   
     
     
         17 . The non-transitory machine-readable medium of  claim 16 , wherein the instructions, when executed by the controller circuitry, cause the controller circuitry to further:
 generate a decrypted second data line by decrypting the corrected second data line.   
     
     
         18 . The non-transitory machine-readable medium of  claim 16 , wherein the third metadata further includes a second part of the second error correction data portion of the second ECC. 
     
     
         19 . The non-transitory machine-readable medium of  claim 13 , wherein the first metadata is proximate to the first data line in the first memory circuitry portion of the memory circuitry. 
     
     
         20 . A system, comprising:
 memory circuitry including a first memory circuitry portion and a second memory circuitry portion sequestered from the first memory circuitry portion; and   controller circuitry to:
 responsive to receipt of a read request generated by an application executed by processor circuitry to read a first data line of a plurality of data lines stored in the first memory circuitry portion, retrieve the first data line and first metadata associated with the first data line from the first memory circuitry portion, wherein the first metadata is to include an error detection data portion of an error correction code (ECC) associated with first data line; 
 determine, based on the error detection data portion of the ECC, whether an error exists in the first data line; 
 responsive to a determination that the first data line contains a first error, retrieve from the second memory circuitry portion, second metadata associated with the first data line and including at least a part of an error correction data portion of the ECC; 
 generate a corrected first data line by correcting at least the first error in the first data line based on the error correction data portion of the ECC; and 
 verify the corrected first data line based on a message authentication code (MAC) associated with the first data line and included in the first metadata. 
   
     
     
         21 . The system of  claim 20 , wherein the controller circuitry is to further:
 responsive to an unsuccessful verification of the corrected first data line, generate a security exception.   
     
     
         22 . The system of  claim 20 , wherein the controller circuitry is to further:
 generate a decrypted first data line by decrypting the corrected first data line.   
     
     
         23 . The system of  claim 22 , wherein the controller circuitry is to further:
 responsive to a successful verification of the corrected first data line, transfer the decrypted first data line to the processor circuitry.   
     
     
         24 . The system of  claim 20 , wherein the first metadata further includes a second part of the error correction data portion of the ECC. 
     
     
         25 . The system of  claim 20 , wherein the first metadata is proximate to the first data line in the first memory circuitry portion of the memory circuitry.