Instruction set architecture with programmable direct memory access and expanded fence/flush operations

Abstract

In one embodiment, a processor includes decode circuitry and memory offload circuitry. The decode circuitry decodes an instruction to perform a direct memory access (DMA) operation, which includes an opcode and one or more fields. The opcode indicates a type of DMA operation to be performed. The one or more fields indicate a destination memory region and one or more data operands. The memory offload circuitry offloads the instruction from an execution pipeline and performs the DMA operation.

1 . A processor, comprising:
 decode circuitry to decode an instruction to perform a direct memory access (DMA) operation, wherein the instruction comprises an opcode and one or more fields, wherein the opcode indicates a type of DMA operation to be performed, and wherein the one or more fields indicate:
 a destination memory region; and 
 one or more data operands; and 
   memory offload circuitry to offload the instruction from an execution pipeline, wherein the memory offload circuitry is to perform the DMA operation based on the opcode and the one or more fields.   
     
     
         2 . The processor of  claim 1 , wherein the one or more fields further indicate:
 a compute operation to be performed on the one or more data operands, wherein one or more resulting data operands are to be written to the destination memory region.   
     
     
         3 . The processor of  claim 2 , wherein the compute operation comprises:
 a complement operation;   a bitwise operation;   an add operation; or   a multiply operation.   
     
     
         4 . The processor of  claim 3 , wherein the compute operation is to be performed on at least one data operand from a source memory region and at least one data operand from the destination memory region. 
     
     
         5 . The processor of  claim 3 , wherein the one or more fields comprise a DMA type field, wherein the DMA type field indicates the compute operation to be performed. 
     
     
         6 . The processor of  claim 1 , wherein:
 the DMA operation is to read from or write to a non-contiguous memory region, wherein the non-contiguous memory region is a source memory region or the destination memory region.   
     
     
         7 . The processor of  claim 1 , wherein the instruction is a DMA initialize instruction, wherein the DMA initialize instruction is to initialize the destination memory region with data. 
     
     
         8 . The processor of  claim 1 , wherein the instruction is a DMA initialize stride instruction, wherein the DMA initialize stride instruction is to initialize the destination memory region with data, wherein the destination memory region is a strided memory region. 
     
     
         9 . The processor of  claim 1 , wherein the instruction is a DMA copy stride instruction, wherein the DMA copy stride instruction is to copy data from a source memory region to the destination memory region, wherein at least one of the source memory region or the destination memory region is a strided memory region. 
     
     
         10 . The processor of  claim 1 , wherein the instruction is a DMA scatter instruction, wherein the DMA scatter instruction is to scatter data across the destination memory region, wherein the destination memory region is a non-contiguous memory region. 
     
     
         11 . The processor of  claim 1 , wherein the instruction is a DMA gather instruction, wherein the DMA gather instruction is to gather data from a source memory region and store the data in the destination memory region, wherein the source memory region is a non-contiguous memory region and the destination memory region is a contiguous memory region. 
     
     
         12 . One or more non-transitory computer-readable media comprising instructions that, when executed or implemented by a processor, cause the processor to:
 decode an instruction to perform a direct memory access (DMA) operation, wherein the instruction comprises an opcode and one or more fields, wherein the opcode indicates a type of DMA operation to be performed, and wherein the one or more fields indicate:
 a destination memory region; and 
 one or more data operands; and 
   offload the instruction from an execution pipeline to a memory offload engine, wherein the memory offload engine is to perform the DMA operation based on the opcode and the one or more fields.   
     
     
         13 . The computer-readable media of  claim 12 , wherein the one or more fields further indicate:
 a compute operation to be performed on the one or more data operands, wherein one or more resulting data operands are to be written to the destination memory region.   
     
     
         14 . The computer-readable media of  claim 13 , wherein the compute operation comprises:
 a complement operation;   a bitwise operation;   an add operation; or   a multiply operation.   
     
     
         15 . The computer-readable media of  claim 14 , wherein the compute operation is to be performed on at least one data operand from a source memory region and at least one data operand from the destination memory region. 
     
     
         16 . The computer-readable media of  claim 12 , wherein:
 the DMA operation is to read from or write to a non-contiguous memory region, wherein the non-contiguous memory region is a source memory region or the destination memory region.   
     
     
         17 . The computer-readable media of  claim 12 , wherein the instruction is a DMA initialize instruction, wherein the DMA initialize instruction is to initialize the destination memory region with data. 
     
     
         18 . The computer-readable media of  claim 12 , wherein the instruction is a DMA initialize stride instruction, wherein the DMA initialize stride instruction is to initialize the destination memory region with data, wherein the destination memory region is a strided memory region. 
     
     
         19 . The computer-readable media of  claim 12 , wherein the instruction is a DMA copy stride instruction, wherein the DMA copy stride instruction is to copy data from a source memory region to the destination memory region, wherein at least one of the source memory region or the destination memory region is a strided memory region. 
     
     
         20 . The computer-readable media of  claim 12 , wherein the instruction is a DMA scatter instruction, wherein the DMA scatter instruction is to scatter data across the destination memory region, wherein the destination memory region is a non-contiguous memory region. 
     
     
         21 . The computer-readable media of  claim 12 , wherein the instruction is a DMA gather instruction, wherein the DMA gather instruction is to gather data from a source memory region and store the data in the destination memory region, wherein the source memory region is a non-contiguous memory region and the destination memory region is a contiguous memory region. 
     
     
         22 . A method, comprising:
 decoding an instruction to perform a direct memory access (DMA) operation, wherein the instruction comprises an opcode and one or more fields, wherein the opcode indicates a type of DMA operation to be performed, and wherein the one or more fields indicate:
 a destination memory region; and 
 one or more data operands; and 
   offloading the instruction from an execution pipeline to a memory offload engine, wherein the memory offload engine is to perform the DMA operation based on the opcode and the one or more fields.   
     
     
         23 . The method of  claim 22 , wherein the one or more fields further indicate:
 a compute operation to be performed on the one or more data operands, wherein one or more resulting data operands are to be written to the destination memory region.   
     
     
         24 . The method of  claim 23 , wherein the compute operation comprises:
 a complement operation;   a bitwise operation;   an add operation; or   a multiply operation.   
     
     
         25 . The method of  claim 22 , wherein the instruction is:
 a DMA initialize instruction, wherein the DMA initialize instruction is to initialize the destination memory region with data;   a DMA initialize stride instruction, wherein the DMA initialize stride instruction is to initialize the destination memory region with data, wherein the destination memory region is a strided memory region;   a DMA copy stride instruction, wherein the DMA copy stride instruction is to copy data from a source memory region to the destination memory region, wherein at least one of the source memory region or the destination memory region is a strided memory region;   a DMA scatter instruction, wherein the DMA scatter instruction is to scatter data across the destination memory region, wherein the destination memory region is a non-contiguous memory region; or   a DMA gather instruction, wherein the DMA gather instruction is to gather data from a source memory region and store the data in the destination memory region, wherein the source memory region is a non-contiguous memory region and the destination memory region is a contiguous memory region.   
     
     
         26 . A computing system, comprising:
 a memory;   a plurality of processing cores, wherein each processing core comprises:
 decode circuitry to decode a plurality of instructions in an execution pipeline, wherein the plurality of instructions comprise a direct memory access (DMA) instruction, wherein the DMA instruction comprises an opcode and one or more fields, wherein the opcode indicates a DMA operation to be performed and the one or more fields indicate:
 a destination memory region on the memory; and 
 one or more data operands; 
 
 execution circuitry to execute the plurality of instructions in the execution pipeline; and 
 memory offload circuitry to offload the DMA instruction from the execution pipeline, wherein the memory offload circuitry is to perform the DMA operation based on the opcode and the one or more fields. 
   
     
     
         27 . The computing system of  claim 26 , wherein the one or more fields further indicate:
 a compute operation to be performed on the one or more data operands, wherein one or more resulting data operands are to be written to the destination memory region.   
     
     
         28 . The computing system of  claim 27 , wherein the compute operation comprises:
 a complement operation;   a bitwise operation;   an add operation; or   a multiply operation.   
     
     
         29 . The computing system of  claim 26 , wherein the instruction is:
 a DMA initialize instruction, wherein the DMA initialize instruction is to initialize the destination memory region with data;   a DMA initialize stride instruction, wherein the DMA initialize stride instruction is to initialize the destination memory region with data, wherein the destination memory region is a strided memory region;   a DMA copy stride instruction, wherein the DMA copy stride instruction is to copy data from a source memory region to the destination memory region, wherein at least one of the source memory region or the destination memory region is a strided memory region;   a DMA scatter instruction, wherein the DMA scatter instruction is to scatter data across the destination memory region, wherein the destination memory region is a non-contiguous memory region; or   a DMA gather instruction, wherein the DMA gather instruction is to gather data from a source memory region and store the data in the destination memory region, wherein the source memory region is a non-contiguous memory region and the destination memory region is a contiguous memory region.