Semiconductor Devices and Methods of Formation

Abstract

Semiconductor devices and methods of forming are described herein. The methods include depositing a dummy gate material layer over a fin etched into a substrate. A gate mask is then formed over the dummy gate material layer in a channel region of the fin. A dummy gate electrode is etched into the dummy gate material using the gate mask. A top spacer is then deposited over the gate mask and along sidewalls of a top portion of the dummy gate electrode. An opening is then etched through the remainder of the dummy gate material and through the fin. A bottom spacer is then formed along a sidewall of the opening and separates a bottom portion of the dummy gate electrode from the opening. A source/drain region is then formed in the opening and the dummy gate electrode is replaced with a metal gate stack.

What is claimed is: 
     
         1 . A method of manufacturing a semiconductor device, the method comprising:
 forming a fin over a substrate;   forming a gate electrode stack over the fin;   forming a first top spacer adjacent to the gate electrode stack;   after forming the first top spacer, forming a first bottom spacer adjacent to the gate electrode stack and between the substrate and the first top spacer; and   forming a first source/drain region adjacent to the fin and isolated from the gate electrode stack by the first bottom spacer.   
     
     
         2 . The method of  claim 1 , wherein the forming the first bottom spacer forms a multi-layer film having a backwards L-shape in a first cross-sectional view. 
     
     
         3 . The method of  claim 1 , wherein the forming the first top spacer forms a multi-layer film having an L-shape in a second cross-sectional view. 
     
     
         4 . The method of  claim 1 , wherein after the forming the gate electrode stack the gate electrode stack has a first width adjacent to the first top spacer and wherein the gate electrode stack has a second width adjacent to the first bottom spacer, the first width being greater than the second width. 
     
     
         5 . The method of  claim 1 , wherein after the forming the gate electrode stack the gate electrode stack has a first width adjacent to the first top spacer and wherein the gate electrode stack has a second width adjacent to the first bottom spacer, the first width being less than the second width. 
     
     
         6 . The method of  claim 5 , wherein the first top spacer comprises a first material and the first bottom spacer comprises a second material different from the first material. 
     
     
         7 . The method of  claim 1 , wherein the first bottom spacer is wider than the first top spacer. 
     
     
         8 . A semiconductor device comprising:
 a fin over a semiconductor substrate;   a gate stack overlying the fin;   a spacer adjacent to the gate stack, the spacer comprising:
 a first spacer in physical contact with the gate stack; and 
 a second spacer in physical contact with both the first spacer and the gate stack, the second spacer being a different material than the first spacer; and 
   a source/drain region adjacent to the spacer.   
     
     
         9 . The semiconductor device of  claim 8 , wherein the first spacer has a first width and the second spacer has a second width less than the first width. 
     
     
         10 . The semiconductor device of  claim 8 , wherein the first spacer has a first width and the second spacer has a second width greater than the first width. 
     
     
         11 . The semiconductor device of  claim 8 , wherein the first spacer has a first width and the second spacer has the first width. 
     
     
         12 . The semiconductor device of  claim 8 , wherein the first spacer comprises a first portion and a second portion, wherein at least one of the first portion and the second portion has an “L” shape. 
     
     
         13 . The semiconductor device of  claim 12 , wherein both the first portion and the second portion have the “L” shape. 
     
     
         14 . The semiconductor device of  claim 13 , wherein the first spacer comprises a third portion and the third portion, the second portion, and the first portion have sidewalls aligned with each other. 
     
     
         15 . A semiconductor device comprising:
 a fin over a substrate;   a gate electrode stack over the fin;   a first top spacer adjacent to the gate electrode stack;   a first bottom spacer below the first top spacer; and   a first source/drain region adjacent to the fin and isolated from the gate electrode stack by the first bottom spacer.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the first top spacer comprises a multi-layer film having an L-shape. 
     
     
         17 . The semiconductor device of  claim 15 , wherein the first bottom spacer comprises a multi-layer film having a backwards L-shape. 
     
     
         18 . The semiconductor device of  claim 15 , wherein the gate electrode stack has a first width adjacent to the first top spacer and wherein the gate electrode stack has a second width adjacent to the first bottom spacer, the first width being greater than the second width. 
     
     
         19 . The semiconductor device of  claim 15 , wherein the gate electrode stack has a first width adjacent to the first top spacer and wherein the gate electrode stack has a second width adjacent to the first bottom spacer, the first width being less than the second width. 
     
     
         20 . The semiconductor device of  claim 15  wherein the first top spacer comprises a first material and the first bottom spacer comprises a second material different from the first material.