Shift register and display device and driving method thereof

Abstract

The power consumption of a shift register or a display device including the shift register is reduced. A clock signal is supplied to a shift register by a plurality of wirings, not by one wiring. Any one of the plurality of wirings supplies a clock signal in only part of the operation period of the shift register, not during the whole operation period of the shift register. Therefore, the capacity load caused with the supply of clock signals can be reduced, leading to reduction in power consumption of the shift register.

1 . (canceled) 
     
     
         2 . A display device, comprising:
 a scanning line drive circuit comprising a plural stage circuits,   wherein one of the plural stage circuits comprises first to sixth transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and another of the source and the drain of the first transistor is electrically connected to a second wiring,   wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, and another of the source and the drain of the second transistor is electrically connected to a third wiring,   wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, and another of the source and the drain of the third transistor is electrically connected to a fourth wiring, and a gate of the third transistor is electrically connected to a fifth wiring,   wherein one of a source and the drain of the fourth transistor is electrically connected to the gate of the first transistor, and another of the source and the drain of the fourth transistor is electrically connected to the third wiring, and the gate of the fourth transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, another of the source and the drain of the sixth transistor is electrically connected to the third wiring, and a gate of the sixth transistor is electrically connected to the fifth wiring,   wherein the one of the plural stage circuits is configured to output a scanning signal to the first wiring,   wherein each of the first to sixth transistors is a bottom gate type transistor,   wherein each of the first to sixth transistors comprises a channel forming region in an oxide semiconductor layer, a first silicon nitride layer below the oxide semiconductor layer, an oxide insulating layer over the oxide semiconductor layer, a second silicon nitride layer over the oxide insulating layer,   wherein, in a plan view, the oxide insulating layer is in contact with the oxide semiconductor layer in a region overlapping the channel forming region, and   wherein, in the plan view, the oxide semiconductor layer is surrounded by a region where the first silicon nitride layer and the second silicon nitride layer overlap, and wherein the second silicon nitride layer does not have a region in contact with the oxide semiconductor layer.   
     
     
         3 . A display device, comprising:
 a scanning line drive circuit comprising a plural stage circuits,   wherein one of the plural stage circuits comprises first to sixth transistor,   wherein one of a source and a drain of the first transistor is electrically connected to a first wiring, and another of the source and the drain of the first transistor is electrically connected to a second wiring,   wherein one of a source and a drain of the second transistor is electrically connected to the first wiring, and another of the source and the drain of the second transistor is electrically connected to a third wiring,   wherein one of a source and a drain of the third transistor is electrically connected to a gate of the first transistor, and another of the source and the drain of the third transistor is electrically connected to a fourth wiring, and a gate of the third transistor is electrically connected to a fifth wiring,   wherein one of a source and the drain of the fourth transistor is electrically connected to the gate of the first transistor, and another of the source and the drain of the fourth transistor is electrically connected to the third wiring, and the gate of the fourth transistor is electrically connected to a gate of the second transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to the gate of the second transistor,   wherein one of a source and a drain of the sixth transistor is electrically connected to the gate of the second transistor, another of the source and the drain of the sixth transistor is electrically connected to the third wiring, and a gate of the sixth transistor is electrically connected to the fifth wiring,   wherein the one of the plural stage circuits is configured to output a scanning signal to the first wiring,   wherein each of the first to sixth transistors is a bottom gate type transistor,   wherein each of the first to sixth transistors comprises a channel forming region in an oxide semiconductor layer, a first silicon nitride layer below the oxide semiconductor layer, an oxide insulating layer over the oxide semiconductor layer, a second silicon nitride layer over the oxide insulating layer,   wherein the oxide semiconductor layer comprises In, Ga, and Zn,   wherein, in a plan view, the oxide insulating layer is in contact with the oxide semiconductor layer in a region overlapping the channel forming region, and   wherein, in the plan view, the oxide semiconductor layer is surrounded by a region where the first silicon nitride layer and the second silicon nitride layer overlap, and wherein the second silicon nitride layer does not have a region in contact with the oxide semiconductor layer.