US2022208996A1PendingUtilityA1

Methods and apparatus for processing a substrate

Assignee: APPLIED MATERIALS INCPriority: Dec 31, 2020Filed: Dec 31, 2020Published: Jun 30, 2022
Est. expiryDec 31, 2040(~14.4 yrs left)· nominal 20-yr term from priority
H10P 95/00H10P 50/282H10D 99/00H10D 86/411H10D 84/83H10D 86/0212H10D 30/0316H10D 30/6732H10D 62/80H10D 30/6755H10D 30/6739H10D 86/60H01L 29/24H01L 21/47635H01L 29/66969H01L 29/4908H01L 29/7869H01L 21/47573H10W 20/42H10W 20/056H10W 20/082
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Claims

Abstract

Methods and apparatus for processing a substrate are provided herein. For example, a method can include depositing a first metal layer on a substrate and etching the first metal layer to form a gate electrode, depositing a dielectric layer atop the gate electrode, depositing a semi-conductive oxide layer atop the dielectric layer to cover a portion of the gate electrode, etching the dielectric layer from a portion of the gate electrode that is not covered by the semi-conductive oxide layer to form a gate access via, and depositing a second metal layer atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.

Claims

exact text as granted — not AI-modified
1 . A method of processing a substrate, comprising:
 depositing a first metal layer on a substrate and etching the first metal layer to form a gate electrode;   depositing a dielectric layer atop the gate electrode;   depositing a semi-conductive oxide layer atop the dielectric layer to cover a portion of the gate electrode;   etching the dielectric layer from a portion of the gate electrode that is not covered by the semi-conductive oxide layer to form a gate access via; and   depositing a second metal layer atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.   
     
     
         2 . The method of  claim 1 , wherein depositing the first metal layer comprises depositing at least one of titanium, copper, or molybdenum. 
     
     
         3 . The method of  claim 1 , wherein the first metal layer has a thickness of about 100 nm. 
     
     
         4 . The method of  claim 1 , wherein depositing the dielectric layer comprises depositing at least one of silicon oxide, silicon nitride, or aluminum nitride. 
     
     
         5 . The method of  claim 1 , wherein the dielectric layer has a thickness of about 200 nm. 
     
     
         6 . The method of  claim 1 , wherein depositing the semi-conductive oxide layer comprises depositing at least one of zinc oxide, aluminum doped zinc oxide (Al—ZO), indium-zinc oxide, indium-gallium-zinc-oxide (IGZO). 
     
     
         7 . The method of  claim 1 , wherein the semi-conductive oxide layer has a thickness of about 50 nm. 
     
     
         8 . The method of  claim 1 , wherein etching the dielectric layer comprises performing a dry etch process. 
     
     
         9 . The method of  claim 1 , wherein depositing the second metal layer comprises depositing at least one of titanium, copper, or molybdenum. 
     
     
         10 . The method of  claim 1 , wherein the second metal layer has a thickness of about 100 nm. 
     
     
         11 . The method of  claim 1 , further comprising depositing a polymer coating layer to cover the second metal layer and etching the polymer coating layer to form vias exposing the second metal layer. 
     
     
         12 . The method of  claim 11 , further comprising depositing a third metal to fill the vias and form an at least one metal contact atop the polymer coating layer. 
     
     
         13 . The method of  claim 12 , further comprising connecting at least one of a digital circuit, a dynamic random-access memory, or an integrated circuit to the at least one metal contact. 
     
     
         14 . The method of  claim 13 , further comprising removing the substrate after connecting the at least one of the digital circuit, the dynamic random-access memory, or the integrated circuit to the at least one metal contact and performing under bump metallization to form solder bumps on a bottom surface of the dielectric layer. 
     
     
         15 . The method of  claim 1 , wherein the substrate is one of a carrier substrate made from silicon, glass or fiberglass, a metal layer of one of a redistribution layer interposer or a substrate interconnect, or at least one of a digital circuit, a dynamic random-access memory, or an integrated circuit. 
     
     
         16 . A non-transitory computer readable storage medium having stored thereon instructions that when executed by a processor performs a method of processing a substrate, comprising:
 depositing a first metal layer on a carrier substrate and etching some of the first metal layer to form a gate electrode;   depositing a dielectric layer atop the gate electrode;   depositing a semi-conductive oxide layer atop the dielectric layer to cover a portion of the gate electrode;   etching the dielectric layer from a portion of the gate electrode that is not covered by the semi-conductive oxide layer to form a gate access via; and   depositing a second metal layer atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.   
     
     
         17 . The non-transitory computer readable storage medium of  claim 16 , wherein depositing the first metal layer comprises depositing at least one of titanium, copper, or molybdenum, and wherein the first metal layer has a thickness of about 100 nm. 
     
     
         18 . The non-transitory computer readable storage medium of  claim 16 , wherein etching some of the first metal layer comprises performing a dry etch process. 
     
     
         19 . The non-transitory computer readable storage medium of  claim 16 , wherein depositing the dielectric layer comprises depositing at least one of silicon oxide, silicon nitride, or aluminum nitride, and wherein the dielectric layer has a thickness of about 200 nm. 
     
     
         20 . An apparatus for use with a thin film transistor, comprising:
 a first metal layer deposited on a carrier substrate and having a gate electrode formed thereon;   a dielectric layer deposited atop the gate electrode;   a semi-conductive oxide layer deposited atop the dielectric layer to cover a portion of the gate electrode;   a gate access formed in a portion of the gate electrode that is not covered by the semi-conductive oxide layer; and   a second metal layer is deposited atop the dielectric layer and the semi-conductive oxide layer, and within the gate access via.

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