Stack packages including a hybrid wire bonding structure

Abstract

A stack package includes first and second sub-chip stacks stacked on a package substrate and bonding wires. The first sub-chip stack includes first and second sub-chips. The first sub-chip has a first surface on which a first common pad is disposed. The second sub-chip has a third surface on which a second common pad is disposed. The third surface is bonded to the first surface such that the second common pad is bonded to the first common pad. The second sub-chip includes a fourth surface opposite to the second common pad and a through hole extending from the fourth surface to reveal the second common pad. The bonding wire is connected to the second common pad via the through hole and electrically connects both of the first and second common pads to the package substrate.

What is claimed is: 
     
         1 . A stack package comprising:
 a first sub-chip stack disposed on a package substrate; and   a bonding wire electrically connecting the first sub-chip stack to the package substrate,   wherein the first sub-chip stack comprises:
 a first sub-chip having a first surface on which a first common pad is disposed; and 
 a second sub-chip having a third surface on which a second common pad is disposed, wherein the third surface is bonded to the first surface such that the second common pad is bonded to the first common pad, 
 wherein the second sub-chip comprises: 
 a fourth surface which is opposite to the second common pad; and 
 a through hole extending from the fourth surface to reveal the second common pad, 
   wherein the bonding wire passes through the through hole and is directly connected to the second common pad.   
     
     
         2 . The stack package of  claim 1 , further comprising a second sub-chip stack disposed on the first sub-chip stack and laterally offset relative to the first sub-chip stack. 
     
     
         3 . The stack package of  claim 2 , wherein the second sub-chip stack has substantially the same shape as the first sub-chip. 
     
     
         4 . The stack package of  claim 2 , wherein the second sub-chip stack comprises:
 a third sub-chip having a fifth surface on which a third discrete pad and a third common pad are disposed and a sixth surface which is opposite to the third discrete pad; and   a fourth sub-chip having a seventh surface bonded to the fifth surface,   wherein the fourth sub-chip comprises:
 a fourth common pad disposed on the seventh surface; and 
 an additional through hole extending from an eighth surface of the fourth sub-chip opposite to the third sub-chip to reveal the fourth common pad. 
   
     
     
         5 . The stack package of  claim 2 , wherein the first sub-chip comprises a first discrete pad receiving a chip enable signal for selecting the first sub-chip of the first and second sub-chips.