Memory system including a memory controller

Abstract

A memory system includes a memory controller, a first memory module including first and second groups of first memory chips, a second memory module including first and second groups of second memory chips, and a channel including a first group of signal lines suitable for coupling the memory controller with the first memory module, and a second group of signal lines suitable for coupling the memory controller with the second memory module.

What is claimed is: 
     
         1 . A memory module, comprising:
 a pool of first volatile memory;   a pool of second volatile memory;   a controller coupled to the pool of first volatile memory and the pool of second volatile memory; and   an interface coupled to the controller,   wherein the pool of first volatile memory has a path selection unit configured to connect electrically between the interface and the pool of second volatile memory.   
     
     
         2 . The memory module of  claim 1 , wherein the path selection unit is configured to selectively connect the interface to one or more second volatile memory in the pool of second volatile memory. 
     
     
         3 . The memory module of  claim 2 , wherein the pool of first volatile memory has both input port and output port separately. 
     
     
         4 . The memory module of  claim 3 , wherein the pool of first volatile memory is adapted to receive data from input port and send data to output port simultaneously. 
     
     
         5 . The memory module of  claim 2 , wherein the pool of second volatile memory has a port for data input and data output alternatively. 
     
     
         6 . The memory module of  claim 1 , wherein the interface includes at least one of a group of signal lines, a data bus, or a path. 
     
     
         7 . A memory system, comprising:
 a first memory module including a plurality of memory chips;   a second memory module including a plurality of memory chips; and   a memory controller communicating with the first memory module and the second memory module via a channel,   wherein the channel includes a first group of signal lines dedicated to the first memory module and a second group of signal lines dedicated to the second memory module.   
     
     
         8 . The memory system of  claim 7 , wherein the memory controller exchanges first data with the first memory module via the first group of signal lines and second data with the second memory module via the second group of signal lines, concurrently. 
     
     
         9 . The memory system of  claim 7 , wherein the memory controller is configured to provide command signal and address signal to the first memory module via the first group of signal lines and to the second memory module via the second group of signal lines. 
     
     
         10 . The memory system of  claim 7 , wherein each memory chip in the first memory module has a port configuration different from the plurality of memory chips in the second memory module. 
     
     
         11 . A memory module, comprising:
 a first memory chip;   a second memory chip coupled to the first memory chip through data bus; and   a path selection unit configured to selectively activate a path for transferring data between the first memory chip and the second memory chip via the data bus.   
     
     
         12 . The memory module of  claim 11 , further comprising:
 a buffer chip configured to buffer data transferred between the first memory chip and an external device.   
     
     
         13 . The memory module of  claim 12 , wherein, when the path selection unit activates the path, the data is transferred from the buffer chip to the second memory chip through the first memory chip. 
     
     
         14 . The memory module of  claim 13 , wherein the path selection unit and the path are included in the first memory chip. 
     
     
         15 . The memory module of  claim 13 , wherein, when the path selection unit deactivates the path, the data transferred from the external device is stored in the first memory chip. 
     
     
         16 . A memory module, comprising:
 a pool of first volatile memory;   a pool of second volatile memory;   a controller coupled to the pool of first volatile memory and the pool of second volatile memory; and   an interface coupled to the controller,   wherein the pool of first volatile memory has a path selection unit configured to selectively connect the interface to one or more second volatile memory in the pool of second volatile memory.