Wireless Circuitry with Self-Calibrated Harmonic Rejection Mixers

Abstract

An electronic device may include a harmonic rejection mixer with a delay line, mixer array, and load. The delay line may generate LO phases. Each mixer in the array may have a first input that receives an LO phase and a second input coupled to an input switch and the first input of the next mixer circuit through an inter-mixer switch. The load may include a set of switches. In a transmit mode, the input switches and set of switches may be closed while the inter-mixer switches are open. In a self-calibration mode, the input switches and set of switches may be open while the inter-mixer switches are closed. A controller may sweep through phase codes for the programmable delay line while storing a digital output from the load. The controller may calibrate the phase code based on the digital output.

What is claimed is: 
     
         1 . A mixer array comprising:
 a first mixer circuit with a first input configured to receive a first local oscillator (LO) phase, a second input coupled to an input path, and a first output coupled to an output path;   a second mixer circuit with a third input configured to receive a second LO phase, a fourth input coupled to the input path, and a second output coupled to the output path; and   a switch coupled between the second input and the third input.   
     
     
         2 . The mixer array of  claim 1  wherein the second LO phase is phase-delayed with respect to the first LO phase. 
     
     
         3 . The mixer array of  claim 1 , wherein the mixer array is configured to receive an input signal on the input path and is configured to produce an output signal on the output path, the output signal having a higher frequency than the input signal. 
     
     
         4 . The mixer array of  claim 3 , wherein the output signal comprises a radio-frequency signal. 
     
     
         5 . The mixer array of  claim 1  further comprising:
 a third mixer circuit having a fifth input configured to receive a third LO phase, a sixth input coupled to the input path, and a third output coupled to the output path; and 
 an additional switch coupled between the fourth input and the fifth input. 
 
     
     
         6 . The mixer array of  claim 5 , wherein the second LO phase is phase-delayed with respect to the first LO phase and the third LO phase is phase-delayed with respect to the first LO phase and the second LO phase. 
     
     
         7 . The mixer array of  claim 1 , wherein the first input and the third input are coupled to a programmable delay line. 
     
     
         8 . The mixer array of  claim 7 , wherein the first input is coupled to a first delay cell in the programmable delay line and the second input is coupled to a second delay cell in the programmable delay line. 
     
     
         9 . The mixer array of  claim 1 , further comprising:
 an additional switch that couples the input path to the second input.   
     
     
         10 . The mixer array of  claim 9 , wherein the mixer array is configured to generate an output signal on the output path while the additional switch is closed and while the switch between the second input and the third input is open. 
     
     
         11 . The mixer array of  claim 10 , wherein the mixer array is configured to generate a direct current (DC) voltage on the output path while the switch between the second input and the third input is closed and while the additional switch is open. 
     
     
         12 . The mixer array of  claim 1 , wherein the output path comprises first and second differential output lines. 
     
     
         13 . A method of operating mixer circuitry comprising:
 with a first mixer circuit, mixing a first LO phase with a second LO phase that is phase-delayed with respect to the first LO phase;   with a second mixer circuit, mixing the second LO phase with a third LO phase that is phase-delayed with respect to the second LO phase;   with at least the first and second mixer circuits, outputting a direct current (DC) voltage onto an output path; and   with a controller, adjusting the first, second, and third LO phases based on the DC voltage on the output path.   
     
     
         14 . The method of  claim 13 , further comprising:
 with an adjustable load coupled to the output path, amplifying the DC voltage to generate an amplified DC voltage.   
     
     
         15 . The method of  claim 14 , further comprising:
 with an analog-to-digital converter (ADC) coupled to the output path, generating a digital output based on the amplified DC voltage.   
     
     
         16 . The method of  claim 14 , further comprising:
 with the controller, adjusting the first, second, and third LO phases based on the digital output.   
     
     
         17 . The method of  claim 15 , wherein adjusting the first LO phase produces a first calibrated LO phase, adjusting the second LO phase produces a second calibrated LO phase, and adjusting the third LO phase produces a third calibrated LO phase, the method further comprising:
 with the first mixer circuit, mixing the first calibrated LO phase with an input signal;   with the second mixer circuit, mixing the second calibrated LO phase with the input signal;   with the first and second mixer circuits, generating radio-frequency signals on the output path based on the input signal, the first calibrated LO phase, and the second calibrated LO phase;   amplifying the radio-frequency signals to produce amplified radio-frequency signals; and   with an antenna, transmitting the amplified radio-frequency signals.   
     
     
         18 . Wireless circuitry comprising:
 an input path;   an output path;   a programmable delay line configured to generate a set of local oscillator (LO) phases;   a mixer array coupled between the input path and the output path, the mixer array being configured to generate a radio-frequency signal on the output path based on an input signal on the input path and based on the set of LO phases; and   an adjustable load coupled to the output path.   
     
     
         19 . The wireless circuitry of  claim 18 , wherein the adjustable load comprises:
 an inductor coupled to the output path;   a first switch coupled in series between the inductor and a circuit node;   a power supply terminal;   a second switch coupled between the power supply terminal and the circuit node;   a transistor coupled between the output path and the power supply terminal, the transistor having a gate terminal coupled to the circuit node; and   a resistor coupled between the inductor and the circuit node in parallel with the first switch.   
     
     
         20 . The wireless circuitry of  claim 18 , further comprising:
 a controller configured to operate the wireless circuitry in a transmit mode and in a calibration mode, wherein the mixer array is configured to output the radio-frequency signal on the output path in the transmit mode and is configured to output a direct-current (DC) voltage on the output path in the calibration mode; and   an analog-to-digital converter (ADC) coupled to the output path, the ADC being configured to generate a digital output based on the DC voltage in the calibration mode, and the controller being configured to adjust the set of LO phases produced by the programable delay line based on the digital output in the calibration mode.