US2022199842A1PendingUtilityA1

Solar cell emitter region fabrication using self-aligned implant and cap

Assignee: SUNPOWER CORPPriority: Dec 9, 2013Filed: Mar 11, 2022Published: Jun 23, 2022
Est. expiryDec 9, 2033(~7.4 yrs left)· nominal 20-yr term from priority
Inventors:Timothy Weidman
H10F 71/137H10F 71/1221H10F 77/14H10F 77/315H10F 77/219H10F 10/14H10F 77/1642H10F 77/311H10F 77/122H10F 10/00H10F 77/215Y02P70/50Y02E10/546Y02E10/547H01L 31/1876H01L 31/068H01L 31/02167H01L 31/022441H01L 31/022433H01L 31/035272H01L 31/182H01L 31/03682H01L 31/04H01L 31/028
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Claims

Abstract

Methods of fabricating solar cell emitter regions using self-aligned implant and cap, and the resulting solar cells, are described. In an example, a method of fabricating an emitter region of a solar cell involves forming a silicon layer above a substrate. The method also involves implanting, through a stencil mask, dopant impurity atoms in the silicon layer to form implanted regions of the silicon layer with adjacent non-implanted regions. The method also involves forming, through the stencil mask, a capping layer on and substantially in alignment with the implanted regions of the silicon layer. The method also involves removing the non-implanted regions of the silicon layer, wherein the capping layer protects the implanted regions of the silicon layer during the removing. The method also involves annealing the implanted regions of the silicon layer to form doped polycrystalline silicon emitter regions.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A solar cell, comprising:
 an N-type doped polycrystalline silicon layer disposed on a first thin oxide layer disposed on a monocrystalline silicon substrate, the N-type doped polycrystalline silicon layer having an upper surface with a first surface area;   a P-type doped polycrystalline silicon layer disposed on a second thin oxide layer disposed on the monocrystalline silicon substrate, the P-type doped polycrystalline silicon layer having an upper surface with a second surface area;   a first conductive capping layer on the N-type doped polycrystalline silicon layer, the first conductive capping layer covering all of the N-type doped polycrystalline silicon layer, and the first conductive capping layer having an upper surface with the first surface area;   a second conductive capping layer on the P-type doped polycrystalline silicon layer, the second conductive capping layer covering all of the P-type doped polycrystalline silicon layer, and the second conductive capping layer having an upper surface with the second surface area;   an insulating layer over the first and second conductive capping layers, the insulating layer having a first opening exposing a portion of but not all of the first surface area of the first conductive capping layer, and the insulating layer having a second opening exposing a portion of but not all of the second surface area of the second conductive capping layer;   a first conductive contact in the first opening and electrically connected to the first conductive capping layer; and   a second conductive contact in the second opening and electrically connected to the second conductive capping layer.   
     
     
         2 . The solar cell of  claim 1 , wherein the first conductive contact is further over a portion of an upper surface of the insulating layer. 
     
     
         3 . The solar cell of  claim 1 , wherein the second conductive contact is further over a portion of an upper surface of the insulating layer. 
     
     
         4 . The solar cell of  claim 1 , wherein the first conductive contact is further over a first portion of an upper surface of the insulating layer, and wherein the second conductive contact is further over a second portion of the upper surface of the insulating layer. 
     
     
         5 . The solar cell of  claim 1 , wherein an interface between the first conductive capping layer and the N-type doped polycrystalline silicon layer includes a metal silicide material. 
     
     
         6 . The solar cell of  claim 1 , wherein an interface between the second conductive capping layer and the P-type doped polycrystalline silicon layer includes a metal silicide material. 
     
     
         7 . The solar cell of  claim 1 , wherein an interface between the first conductive capping layer and the N-type doped polycrystalline silicon layer includes a first metal silicide material, and wherein an interface between the second conductive capping layer and the P-type doped polycrystalline silicon layer includes a second metal silicide material. 
     
     
         8 . The solar cell of  claim 1 , wherein the first conductive capping layer comprises a metal selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni) and cobalt (Co). 
     
     
         9 . The solar cell of  claim 1 , wherein the second conductive capping layer comprises a metal selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni) and cobalt (Co). 
     
     
         10 . The solar cell of  claim 1 , wherein the first conductive capping layer comprises a first metal selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni) and cobalt (Co), and wherein the second conductive capping layer comprises a second metal selected from the group consisting of titanium (Ti), zirconium (Zr), hafnium (Hf), niobium (Nb), tantalum (Ta), molybdenum (Mo), tungsten (W), nickel (Ni) and cobalt (Co). 
     
     
         11 . An in-line process apparatus for fabricating an emitter region of a solar cell, the in-line process apparatus comprising:
 a first station configured to align a stencil mask with a substrate;   a second station configured to implant dopant impurity atoms above the substrate, through the stencil mask; and   a third station configured to form a capping layer above the substrate, through the stencil mask, wherein the stencil mask and the substrate are configured to move together through the second and third stations.   
     
     
         12 . The in-line process apparatus of  claim 11 , wherein the first station is further configured to align the stencil mask in contact with or in close proximity to the substrate. 
     
     
         13 . The in-line process apparatus of  claim 11 , wherein the second station comprises an ion-implantation or plasma immersion implantation chamber. 
     
     
         14 . The in-line process apparatus of  claim 11 , wherein the third station comprises a deposition chamber selected from the group consisting of a low pressure chemical vapor deposition (LPCVD), a plasma enhanced chemical vapor deposition (PECVD) chamber, a high density plasma chemical vapor deposition (HDPCVD) chamber and a physical vapor deposition (PVD) chamber.

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