Formation method of chip package

Abstract

A method for forming a chip package is provided. The method includes forming a plurality of conductive structures over a carrier substrate. The method also includes disposing a semiconductor die over the carrier substrate such that the conductive ti structures surround the semiconductor die. The method further includes disposing a shielding element over the semiconductor die and the conductive structures. The shielding element is electrically connected to the conductive structures.

What s claimed is: 
     
         1 . A method for forming a chip package, comprising:
 forming a plurality of conductive structures over a carrier substrate;   disposing a semiconductor die over the carrier substrate such that the conductive structures surround the semiconductor die; and   disposing a shielding element over the semiconductor die and the conductive structures, wherein the shielding element is electrically connected to the conductive structures.   
     
     
         2 . The method as claimed in  claim 1 , further comprising:
 forming a protective layer to surround the conductive structures and the semiconductor die; and   bonding a protective substrate to the conductive structures before the a protective layer is formed.   
     
     
         3 . The method as claimed in  claim 2 , further comprising forming the shielding element over the protective substrate before bonding the protective substrate to the conductive structures. 
     
     
         4 . The method as claimed in  claim 2 , further comprising forming an antenna element over the protective substrate. 
     
     
         5 . The method as claimed in  claim 4 , wherein the antenna element is formed over the protective substrate before bonding the protective substrate to the conductive structures. 
     
     
         6 . The method as claimed in  claim 2 , wherein the protective substrate is bonded to the conductive structures through tin-containing solder elements. 
     
     
         7 . The method as claimed in  claim 2 , further comprising:
 introducing a polymer material between the protective substrate and the carrier substrate; and   curing the polymer material to form the protective layer.   
     
     
         8 . The method as claimed in  claim 2 , further comprising forming a redistribution structure over the carrier substrate before the conductive structures are formed. 
     
     
         9 . The method as claimed in  claim 8 , further comprising:
 removing the carrier substrate; and   forming conductive bumps over the redistribution structure, wherein the redistribution structure is between the protective layer and the conductive bumps.   
     
     
         10 . The method as claimed in  claim 2 , further comprising disposing an additional semiconductor die over the carrier substrate before the protective layer is formed, wherein the additional semiconductor die is outside of an area surrounded by the conductive structures. 
     
     
         11 . The method as claimed in  claim 1 , wherein the shielding element comprises a conductive plate, a conductive mesh, or a combination thereof. 
     
     
         12 . The method as claimed in  claim 1 , wherein two of the conductive structures are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die. 
     
     
         13 . A method for forming a chip package, comprising:
 forming a plurality of conductive structures over a redistribution structure; and   disposing a semiconductor die over the redistribution structure such that the conductive structures surround the semiconductor die;   wherein two of the conductive structures are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the semiconductor die.   
     
     
         14 . The method as claimed in  claim 13 , wherein each of the conductive structures has a width in a range from about 5 μm to about ten times the distance. 
     
     
         15 . The method as claimed in  claim 13 , further comprising:
 forming a protective layer to surround the conductive structures and the semiconductor die; and   bonding a protective substrate to the conductive structures before the protective layer is formed.   
     
     
         16 . The method as claimed in  claim 15 , further comprising forming a shielding element over the protective substrate before bonding the protective substrate to the conductive structures. 
     
     
         17 . A method for forming a chip package, comprising:
 disposing a first semiconductor die and a second semiconductor die over the a redistribution structure; and   disposing a plurality of conductive structures over the redistribution structure;   wherein the conductive structures surround an area where the first semiconductor die is positioned, and the second semiconductor die is positioned outside of the area.   
     
     
         18 . The method as claimed in  claim 17 , wherein two of the conductive structures are separated from each other by a distance, and the distance is smaller than half a wavelength of an electromagnetic wave generated by the first semiconductor die. 
     
     
         19 . The method as claimed in  claim 17 , further comprising disposing a shielding element over the first semiconductor die, wherein the shielding element is electrically connected to the conductive structures. 
     
     
         20 . The method as claimed in  claim 19 , wherein the shielding element comprises a conductive mesh having a plurality of through-holes, and each of the through-holes has a width that is smaller than half the wavelength of the electromagnetic wave generated by the first semiconductor die.