Passivation layer for an integrated circuit device that provides a moisture and proton barrier

Abstract

An integrated circuit device includes a metal contact and a passivation layer extending on a sidewall of the metal contact and on first and second surface portions of a top surface of the metal contact. The passivation layer is format by a stack of layers including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and a Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and PTEOS layers extend over the first surface portion, but not the second surface portion, of the top surface of the metal contact. The Silicon-rich Nitride layer extends over both the first and second surface portions, and is in contact with the second surface portion.

What is claimed is: 
     
         1 . An integrated circuit device, comprising:
 a metal contact having a top surface, the top surface of the metal contact including a first surface portion, a second surface portion and a third surface portion; and   a passivation layer extending on the first and second surface portions of the top surface of the metal contact;   wherein the passivation layer comprises a stack of layers including:
 a tetraethyl orthosilicate (TEOS) layer; 
 a Phosphorus doped TEOS (PTEOS) layer on top of the TEOS layer; and 
 a high-density Silicon-rich Nitride layer on top of the PTEOS layer; 
   wherein the TEOS and PTEOS layers extend over the first surface portion of the top surface of the metal contact, but not over the second and third surface portions of the top surface of the metal contact; and   wherein the high-density Silicon-rich Nitride layer extends over the first and second surface portions of the top surface of the metal contact, but not over the third surface portion of the top surface of the metal contact.   
     
     
         2 . The integrated circuit device of  claim 1 , wherein the high-density Silicon-rich Nitride layer is in contact with the second surface portion of the top surface of the metal contact. 
     
     
         3 . The integrated circuit device of  claim 1 , wherein the high-density Silicon-rich Nitride layer is in contact with side edge surfaces of the TEOS and PTEOS layers at a transition from the first surface portion to the second surface portion. 
     
     
         4 . The integrated circuit device of  claim 1 , wherein the TEOS layer is in contact with the first surface portion of the top surface of the metal contact. 
     
     
         5 . The integrated circuit device of  claim 1 , further comprising a Silicon flash layer in the stack of layers for the passivation layer, wherein said Silicon flash layer is positioned between the PTEOS layer and the high-density Silicon-rich Nitride layer. 
     
     
         6 . The integrated circuit device of  claim 5 , wherein the Silicon flash layer has a thickness of less than 100 Å. 
     
     
         7 . The integrated circuit device of  claim 5 , wherein the Silicon flash layer is in contact with the second surface portion of the top surface of the metal contact. 
     
     
         8 . The integrated circuit device of  claim 5 , wherein the Silicon flash layer is in contact with side edge surfaces of the TEOS and PTEOS layers at a transition from the first surface portion to the second surface portion. 
     
     
         9 . The integrated circuit device of  claim 5 , wherein the high-density Silicon-rich Nitride layer is in contact with the Silicon flash layer. 
     
     
         10 . The integrated circuit device of  claim 1 , wherein the TEOS layer has a thickness in a range of about 12,000-16,000 Å. 
     
     
         11 . The integrated circuit device of  claim 1 , wherein the PTEOS layer has a thickness in a range of about 4,000-6,000 Å. 
     
     
         12 . The integrated circuit device of  claim 1 , wherein the high-density Silicon-rich Nitride layer has a thickness in a range of about 8,000-12,000 Å. 
     
     
         13 . The integrated circuit device of  claim 1 , wherein the high-density Silicon-rich Nitride layer has a ratio of N/Si that is less than about 1.3 and the high-density Silicon-rich Nitride layer has a refractive index greater than 2. 
     
     
         14 . The integrated circuit device of  claim 1 , wherein a stoichiometry of the high-density Silicon-rich Nitride layer comprises Si x N y  where x:y is greater than or equal to 3:4 and the high-density Silicon-rich Nitride layer has a refractive index greater than 2. 
     
     
         15 . The integrated circuit device of  claim 1 , wherein the metal contact extends over a premetallization dielectric layer. 
     
     
         16 . The integrated circuit device of  claim 12 , wherein the premetallization dielectric layer is formed solely of TEOS. 
     
     
         17 . The integrated circuit device of  claim 1 , wherein the metal contact is a gate contact of a discrete transistor. 
     
     
         18 . The integrated circuit device of  claim 1 , wherein the metal contact is a source contact of a discrete transistor. 
     
     
         19 . The integrated circuit device of  claim 1 , wherein the metal contact includes a sidewall, and wherein the passivation layer further extends on the sidewall of the metal contact. 
     
     
         20 . The integrated circuit device of  claim 1 , wherein the metal contact is a contact for a transistor source or gate terminal. 
     
     
         21 . The integrated circuit device of  claim 1 , wherein the metal contact is a contact for a transistor emitter or base terminal. 
     
     
         22 . The integrated circuit device of  claim 1 , wherein the metal contact is a contact for an anode or cathode terminal of a diode.