Beol metallization formation

Abstract

A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an inter-layer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

1 . A semiconductor structure for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes, the semiconductor structure comprising:
 a first metallization level including a plurality of conductive lines; and   a second metallization level including a plurality of conductive pillars,   wherein the plurality of conductive pillars are fully aligned with the plurality of conductive lines and a height of the plurality of conductive lines is predetermined.   
     
     
         2 . The semiconductor structure of  claim 1 , wherein the plurality of conductive pillars directly contact a top surface of the plurality of conductive lines. 
     
     
         3 . The semiconductor structure of  claim 1 , wherein the plurality of conductive lines include ruthenium (Ru). 
     
     
         4 . The semiconductor structure of  claim 3 , wherein the plurality of conductive pillars include Ru. 
     
     
         5 . The semiconductor structure of  claim 1 , wherein a width of the plurality of conductive pillars is equal to a width of the of the plurality of conductive lines. 
     
     
         6 . The semiconductor structure of  claim 1 , wherein the plurality of conductive pillars are horizontally offset with respect to each other. 
     
     
         7 . The semiconductor structure of  claim 1 , wherein a low-k dielectric directly contacts sidewalls of the plurality of conductive pillars. 
     
     
         8 . The semiconductor structure of  claim 7 , wherein a height of the low-k dielectric corresponds to a height of the plurality of conductive pillars. 
     
     
         9 . The semiconductor structure of  claim 1 , wherein a different number of conductive pillars are formed on different conductive lines of the plurality of conductive lines. 
     
     
         10 . The semiconductor structure of  claim 1 , wherein pillars along a conductive line of the plurality of conductive lines are not equidistant with respect to each other. 
     
     
         11 . A semiconductor structure comprising:
 a plurality of conductive lines; and   a plurality of conductive pillars,   wherein the plurality of conductive pillars are aligned with the plurality of conductive lines to define multiple T-shaped configurations across a length of the structure.   
     
     
         12 . The semiconductor structure of  claim 11 , wherein the plurality of conductive pillars directly contact a top surface of the plurality of conductive lines. 
     
     
         13 . The semiconductor structure of  claim 11 , wherein the plurality of conductive lines include ruthenium (Ru). 
     
     
         14 . The semiconductor structure of  claim 13 , wherein the plurality of conductive pillars include Ru. 
     
     
         15 . The semiconductor structure of  claim 11 , wherein a width of the plurality of conductive pillars is equal to a width of the of the plurality of conductive lines. 
     
     
         16 . The semiconductor structure of  claim 11 , wherein the plurality of conductive pillars are horizontally offset with respect to each other. 
     
     
         17 . The semiconductor structure of  claim 11 , wherein a low-k dielectric directly contacts sidewalls of the plurality of conductive pillars. 
     
     
         18 . The semiconductor structure of  claim 17 , wherein a height of the low-k dielectric corresponds to a height of the plurality of conductive pillars. 
     
     
         19 . The semiconductor structure of  claim 11 , wherein a different number of conductive pillars are formed on different conductive lines of the plurality of conductive lines. 
     
     
         20 . The semiconductor structure of  claim 11 , wherein pillars along a conductive line of the plurality of conductive lines are not equidistant with respect to each other.