Margin Test Methods and Circuits

Abstract

Described are methods and circuits for margin testing digital receivers. These methods and circuits prevent margins from collapsing in response to erroneously received data and can thus be used in receivers that employ historical data to reduce intersymbol interference (ISI). Some embodiments detect receive errors for input data streams of unknown patterns and can thus be used for in-system margin testing. Such systems can be adapted to dynamically alter system parameters during device operation to maintain adequate margins despite fluctuations in the system noise environment due to e.g. temperature and supply-voltage changes. Also described are methods of plotting and interpreting filtered and unfiltered error data generated by the disclosed methods and circuits. Some embodiments filter error data to facilitate pattern-specific margin testing.

1 . (canceled) 
     
     
         2 . A digital receiver comprising:
 a first sampler having a first sampler input to receive an input signal, a first timing input, and a first sampler output, the first sampler to issue first samples of the input signal;   a second sampler having a second sampler input coupled to the first sampler input to receive the input signal, a second timing input, and a second sampler output, the second sampler to issue second samples of the input signal;   a comparison circuit having a first comparison-circuit input coupled to the first sampler output, a second comparison-circuit input coupled to the second sampler output, and a comparison-circuit output, the comparison circuit to issue an error signal responsive to mismatches between the first samples of the input signal and the second samples of the input signal; and   a multiplexer having a first multiplexer input coupled to the first sampler output, a second multiplexer input connected to the second sampler output, a select terminal, and a multiplexer output.   
     
     
         3 . The digital receiver of  claim 2 , wherein the first sampler, the second sampler, and the comparison circuit are disposed on a semiconductor chip. 
     
     
         4 . The digital receiver of  claim 2 , the comparison circuit to compare the first samples of the input signal with expected samples. 
     
     
         5 . The digital receiver of  claim 2 , the comparison circuit to issue an error signal in response to each mismatch between the first samples and the second samples. 
     
     
         6 . The digital receiver of  claim 2 , further comprising clock control circuitry coupled to the first timing input and the second timing input, the clock control circuitry to vary a first phase of a first clock signal applied the first timing input relative to a second phase of a second clock signal applied to the second timing input. 
     
     
         7 . The digital receiver of  claim 6 , wherein the clock control circuitry varies a phase of the first clock signal in response to a timing control signal. 
     
     
         8 . The digital receiver of  claim 2 , further comprising a third sampler having a third sampler input to receive the input signal, a third timing input, and a third sampler output. 
     
     
         9 . The digital receiver of  claim 2 , wherein the first multiplexer input is coupled to the first sampler output via the comparison circuit. 
     
     
         10 . A digital receiver comprising:
 a first sampler having a first sampler input, a first timing input, and a first sampler output;   a second sampler having a second sampler input coupled to the first sampler input, a second timing input and a second sampler output;   a comparison circuit having a first comparison-circuit input coupled to the first sampler output, a second comparison-circuit input coupled to the second sampler output, and a comparison-circuit output; and   a multiplexer having a first multiplexer input coupled to the first sampler output, a second multiplexer input connected to the second sampler output, a select terminal, and a multiplexer output coupled to the first comparison-circuit input.   
     
     
         11 . The digital receiver of  claim 10 , wherein the first sampler includes a first reference terminal to receive a first reference voltage and the second sampler includes a second reference terminal to receive a second reference voltage distinct from the first reference voltage. 
     
     
         12 . The digital receiver of  claim 11 , wherein the first and second reference voltages are independently adjustable. 
     
     
         13 . The digital receiver of  claim 10 , wherein the first sampler samples an input signal using a first clock signal having a first clock phase and the second sampler samples the input signal using a second clock signal having a second clock phase. 
     
     
         14 . The digital receiver of  claim 13 , wherein the first and second clock phases are independently adjustable. 
     
     
         15 . The digital receiver of  claim 10 , the comparison circuit to compare first samples from the first sampler output with expected samples. 
     
     
         16 . A digital receiver comprising:
 a first sampler having a first sampler input, a first timing input, and a first sampler output;   a second sampler having a second sampler input coupled to the first sampler input, a second timing input and a second sampler output;   a comparison circuit having a first comparison-circuit input coupled to the first sampler output, a second comparison-circuit input coupled to the second sampler output, and a comparison-circuit output;   a first multiplexer having a first multiplexer input coupled to the first sampler output, a second multiplexer input connected to the second sampler output, and a first multiplexer output coupled to the first comparison-circuit input; and   a second multiplexer having a third multiplexer input coupled to the first sampler output, a fourth multiplexer input connected to the second sampler output, and a second multiplexer output coupled to the second comparison-circuit input.   
     
     
         17 . The digital receiver of  claim 16 , wherein the first sampler includes a first reference terminal to receive a first reference voltage and the second sampler includes a second reference terminal to receive a second reference voltage distinct from the first reference voltage. 
     
     
         18 . The digital receiver of  claim 17 , wherein the first and second reference voltages are independently adjustable. 
     
     
         19 . The digital receiver of  claim 16 , wherein the first sampler samples an input signal using a first clock signal having a first clock phase and the second sampler samples the input signal using a second clock signal having a second clock phase. 
     
     
         20 . The digital receiver of  claim 19 , wherein the first and second clock phases are independently adjustable. 
     
     
         21 . The digital receiver of  claim 16 , the comparison circuit to compare first samples from the first sampler output with expected samples.