US2022173244A1PendingUtilityA1

Method for Fabricating a Semiconductor Device

Assignee: UNITED MICROELECTRONICS CORPPriority: Aug 2, 2019Filed: Feb 14, 2022Published: Jun 2, 2022
Est. expiryAug 2, 2039(~13 yrs left)· nominal 20-yr term from priority
Inventors:Tsung-Hsun Tsai
H10P 70/23H10P 14/6544H10P 14/414H10P 50/283H10D 84/83H10D 64/62H10D 62/83H10D 64/021H10D 64/015H10D 84/0147H10D 84/013H10D 84/038H10D 84/0128H10D 30/792Y02P80/30H01L 21/0206H01L 29/456H01L 29/7843H01L 21/02356H01L 21/32053H01L 27/088
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Claims

Abstract

A new method for fabricating a semiconductor device with high selection phosphoric acid solution and eliminating the step of oxide removal and thus reducing oxide loss to improve yield gain and cost saving.

Claims

exact text as granted — not AI-modified
What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a substrate having a first semiconductor device in a first region and a second semiconductor device in a second region;   a stressed oxide layer on the second semiconductor device in the second region;   a silicide blocking layer on the stressed oxide layer in the second region; and   a cap layer on the first semiconductor device in the first region and on the silicide blocking layer in the second region.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the first semiconductor device comprises a gate structure, a source region and a drain region in the substrate on opposite sides of the gate structure, and a silicide layer on the source region and the drain region. 
     
     
         3 . The semiconductor device of  claim 2 , wherein the silicide layer is further formed on the gate structure. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the second semiconductor device comprises a transistor or a resistor without silicide formed thereon. 
     
     
         5 . The semiconductor device of  claim 1 , wherein the stressed oxide layer is coextensive with the silicide blocking layer. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the silicide blocking layer comprises silicon nitride, silicon-rich oxide, SiO 2 , SiON, or SiO 2 /SiN/SiO 2  (ONO structure). 
     
     
         7 . The semiconductor device of  claim 1 , wherein the cap layer is a silicon nitride layer or a double-layer structure comprising a silicon nitride layer and a silicon oxide layer positioned vertically below the silicon nitride layer. 
     
     
         8 . The semiconductor device of  claim 1 , wherein the stressed oxide layer is originally grown and never removed.

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