Breakdown Resistant HEMT Substrate and Device

Abstract

A method includes forming a silicon substrate including first and second substrate layers, the first substrate layer extending to the rear surface, the second substrate layer extending to a first side of the silicon substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer, forming a nucleation region on the first side of the silicon substrate, the nucleation region including a nitride layer, forming a lattice transition layer on the nucleation region, the lattice transition layer being configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure, and epitaxially growing a type III-V semiconductor nitride region on the lattice transition layer.

What is claimed is: 
     
         1 . A method of forming a semiconductor device in a compound semiconductor device structure having a main surface and a rear surface opposite the main surface, the method comprising:
 forming a silicon substrate comprising first and second substrate layers, the first substrate layer extending to the rear surface, the second substrate layer extending to a first side of the silicon substrate that is opposite from the rear surface such that the first substrate layer is completely separated from the first side by the second substrate layer;   forming a nucleation region on the first side of the silicon substrate, the nucleation region comprising a nitride layer;   forming a lattice transition layer on the nucleation region, the lattice transition layer being configured to alleviate stress arising in the silicon substrate due to lattice mismatch between the silicon substrate and other layers in the compound semiconductor device structure; and   epitaxially growing a type III-V semiconductor nitride region on the lattice transition layer.   
     
     
         2 . The method of  claim 1 , wherein forming the nucleation region comprises:
 forming a first nitride layer on the first side of the silicon substrate;   forming a first type III-V semiconductor nitride layer on the first nitride layer; and   forming a second nitride layer on the first type III-V semiconductor nitride layer.   
     
     
         3 . The method of  claim 2 , wherein forming the nucleation region further comprises:
 forming a second type III-V semiconductor nitride layer on the second nitride layer; and   forming a third nitride layer on the second type III-V semiconductor nitride layer.   
     
     
         4 . The method of  claim 1 , wherein forming the silicon substrate comprises:
 providing a substrate with an n-type majority carrier concentration; and   implanting p-type dopants at a lateral surface of the substrate, the p-type dopants extending into the substrate, so as to form the second substrate layer.   
     
     
         5 . The method of  claim 1 , wherein forming the silicon substrate comprises:
 providing a substrate with a p-type majority carrier concentration; and   implanting p-type dopants at a lateral surface of the substrate, the p-type dopants extending into the substrate, so as to form the second substrate layer, the second substrate layer being more highly doped than the first substrate layer.   
     
     
         6 . The method of  claim 1 , wherein forming the silicon substrate comprises:
 providing a substrate with an n-type majority carrier concentration or a p-type type majority carrier concentration; and   epitaxially growing a p-type layer on the substrate.   
     
     
         7 . The method of  claim 1 , wherein epitaxially growing the type III-V semiconductor nitride region comprises epitaxially growing a buffer layer on the lattice transition layer, and epitaxially growing a barrier layer on the barrier layer, the barrier layer having a different band gap than the buffer layer, wherein a two-dimensional charge carrier gas channel arises along an interface between the buffer layer and the barrier layer, and wherein the method further comprises forming a high electron mobility semiconductor device in the type III-V semiconductor nitride region that is configured to control a conduction state of the two-dimensional charge carrier gas channel. 
     
     
         8 . The method of  claim 1 , wherein the second substrate layer is configured to suppress an inversion layer in the silicon substrate arising at an interface between the silicon substrate and the nucleation region. 
     
     
         9 . The method of  claim 1 , wherein the nucleation region is formed directly on the first side of the silicon substrate. 
     
     
         10 . The method of  claim 9 , wherein the nucleation region comprises a first layer of aluminum nitride, a second layer of aluminum nitride, and a first layer of type III-V semiconductor nitride, wherein the first layer of type III-V semiconductor nitride is disposed between the first and second layers of aluminum nitride, and wherein the wherein the first layer of aluminum nitride is in direct contact with the first side of the silicon substrate. 
     
     
         11 . The method of  claim 9 , wherein the lattice transition layer comprises a type III-V semiconductor nitride.