Semiconductor memory device, memory system, and defect detection method

Abstract

A semiconductor memory device includes: a first wiring and a second wiring; a first selection transistor, a memory transistor, and a second selection transistor connected between the first wiring and the second wiring; and a third wiring and a fourth wiring connected to gate electrodes of the first selection transistor and the second selection transistor. From a first timing to a second timing, a first voltage that turns the first selection transistor ON is supplied to the third wiring, and a second voltage that turns the second selection transistor OFF is supplied to the fourth wiring. From the second timing to a third timing, a third voltage that turns the first selection transistor OFF is supplied to the third wiring, and at a fourth timing between the first timing and the third timing, at least one of a voltage and a current of the first wiring is detected.

What is claimed is: 
     
         1 . A semiconductor memory device, comprising:
 a first wiring and a second wiring;   a memory transistor connected between the first wiring and the second wiring;   a first selection transistor connected between the first wiring and the memory transistor;   a second selection transistor connected between the second wiring and the memory transistor;   a third wiring connected to a gate electrode of the first selection transistor;   a fourth wiring connected to a gate electrode of the second selection transistor; and   circuitry configured to
 from a first timing to a second timing, supply a first voltage that turns the first selection transistor ON to the third wiring, and not supply a second voltage that turns the first selection transistor OFF to the third wiring, 
 from the first timing to the second timing, not supply a third voltage that turns the second selection transistor ON to the fourth wiring, and supply a fourth voltage that turns the second selection transistor OFF to the fourth wiring, 
 from the second timing to a third timing, not supply the first voltage to the third wiring, and supply the second voltage to the third wiring, and 
 at a fourth timing between the first timing and the third timing, detect at least one of a voltage and a current of the first wiring. 
   
     
     
         2 . The semiconductor memory device according to  claim 1 , further comprising a fifth wiring connected to a gate electrode of the memory transistor,
 wherein the circuitry is further configured to, at a predetermined timing between the first timing and the second timing, supply a potential difference to the first wiring and the fifth wiring.   
     
     
         3 . The semiconductor memory device according to  claim 1 , further comprising:
 a sense transistor including a gate electrode connected to the first wiring;   a latch circuit connected to the sense transistor;   a switch transistor connected between the sense transistor and the latch circuit; and   a sixth wiring connected to a gate electrode of the switch transistor,   wherein the circuitry is further configured to, at the fourth timing, supply a fifth voltage that turns the switch transistor ON to the sixth wiring.   
     
     
         4 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of the memory transistors connected between the first selection transistor and the second selection transistor; and   a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors,   wherein the circuitry is further configured to, at a predetermined timing between the first timing and the second timing, supply a sixth voltage to a plurality of the fifth wirings.   
     
     
         5 . The semiconductor memory device according to  claim 4 , wherein the sixth voltage is a ground voltage or a voltage larger than the ground voltage. 
     
     
         6 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of the memory transistors connected between the first selection transistor and the second selection transistor; and   a plurality of fifth wirings connected to respective gate electrodes of the plurality of memory transistors, wherein   the circuitry is further configured to
 supply a seventh voltage to a plurality of the fifth wirings, 
 repeatedly perform a process that selects one of the fifth wirings from the plurality of fifth wirings, a process that switches a voltage of the selected fifth wiring to an eighth voltage different from the seventh voltage, and a process that detects at least one of a voltage and a current of the first wiring, and 
 output information configured to specify the fifth wiring corresponding to a timing at which the at least one of the voltage and the current of the first wiring detected has changed. 
   
     
     
         7 . The semiconductor memory device according to  claim 6 , wherein the eighth voltage is a ground voltage or a voltage larger than the ground voltage. 
     
     
         8 . The semiconductor memory device according to  claim 1 , further comprising:
 a plurality of the first wirings;   a plurality of the memory transistors connected between the plurality of first wirings and the second wiring;   a plurality of first selection transistors connected between the plurality of first wirings and the plurality of memory transistors; and   a plurality of second selection transistors connected between the second wiring and the plurality of memory transistors, wherein   the third wiring is commonly connected to gate electrodes of the plurality of first selection transistors,   the fourth wiring is commonly connected to gate electrodes of the plurality of second selection transistors,   the circuitry is further configured to, at the fourth timing, detect at least one of voltages and currents of the plurality of first wirings, and   the semiconductor memory device outputs information corresponding to the at least one of the voltages and the currents of the plurality of first wirings detected.   
     
     
         9 . The semiconductor memory device according to  claim 1 , further comprising:
 a fifth wiring connected to a gate electrode of the memory transistor, wherein   the semiconductor memory device is configured to execute a write operation that writes data into the memory transistor, and   the write operation includes:
 a voltage application operation that supplies a program voltage to the fifth wiring at a fifth timing before the first timing; and 
 an information output operation that outputs information indicative of a state of the write operation at a sixth timing after the third timing. 
   
     
     
         10 . The semiconductor memory device according to  claim 1 , wherein
 the semiconductor memory device is configured to execute an erase operation that erases data from the memory transistor, and   the erase operation includes:
 a voltage application operation that supplies an erase voltage to the second wiring at a seventh timing before the first timing; and 
 an information output operation that outputs information indicative of a state of the erase operation at an eighth timing after the third timing. 
   
     
     
         11 . A memory system, comprising:
 a semiconductor memory device and a control device connected to the semiconductor memory device, wherein   the semiconductor memory device includes:
 a first wiring and a second wiring; 
 a memory transistor connected between the first wiring and the second wiring; 
 a first selection transistor connected between the first wiring and the memory transistor; 
 a second selection transistor connected between the second wiring and the memory transistor; 
 a third wiring connected to a gate electrode of the first selection transistor; 
 a fourth wiring connected to a gate electrode of the second selection transistor; and 
 a fifth wiring connected to a gate electrode of the memory transistor, wherein 
   the semiconductor memory device is configured to execute at least one of a write operation that writes data into the memory transistor and an erase operation that erases data from the memory transistor, and   in the at least one of the write operation and the erase operation,
 supply a program voltage or an erase voltage to the fifth wiring or the second wiring at a first timing, 
 supply a first voltage that turns the first selection transistor ON to the third wiring, and not supply a second voltage that turns the first selection transistor OFF to the third wiring from a second timing after the first timing to a third timing, 
 not supply a third voltage that turns the second selection transistor ON to the fourth wiring, and supply a fourth voltage that turns the first selection transistor OFF to the fourth wiring from the second timing to the third timing, 
 not supply the first voltage to the third wiring, and supply the second to the third wiring from the third timing to a fourth timing, 
 detect at least one of a voltage and a current of the first wiring at a fifth timing between the second timing and the fourth timing, and 
 output information indicative of a state of the write operation or the erase operation at a sixth timing after the fifth timing, wherein 
   the control device is configured to receive the information indicative of the state from the semiconductor memory device, and control the semiconductor memory device based on the information indicative of the state.