Neural network circuit

Abstract

A neural network circuit 201 is a neural network circuit divides convolution operation into convolution operation in a spatial direction and convolution operation in a channel direction, performs the respective convolution operation separately, and includes a 1×1 convolution operation circuit 10 that performs convolution in the channel direction, an SRAM 20 in which a computation result of the 1×1 convolution operation circuit 10 is stored, and an N×N convolution operation circuit 30 that performs convolution in the spatial direction for the computation result stored in the SRAM 20.

What is claimed is: 
     
         1 . A neural network circuit that divides convolution operation into convolution operation in a spatial direction and convolution operation in a channel direction, and performs the respective convolution operation separately, comprising:
 a 1×1 convolution operation circuit that performs convolution in the channel direction;   an SRAM in which a computation result of the 1×1 convolution operation circuit is stored; and   an N×N convolution operation circuit that performs convolution in the spatial direction for the computation result stored in the SRAM.   
     
     
         2 . The neural network circuit according to  claim 1 , further comprising
 a DRAM in which a computation result of the N×N convolution operation circuit is stored,   wherein the 1×1 convolution operation circuit performs the convolution in the channel direction for the computation result stored in the DRAM.   
     
     
         3 . The neural network circuit according to  claim 1 ,
 wherein N is 3.   
     
     
         4 . The neural network circuit according to  claim 1 ,
 wherein the number of calculators in the 1×1 convolution operation circuit and the number of calculators in the N×N convolution operation circuit are set according to a computation cost.   
     
     
         5 . The neural network circuit according to  claim 4 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit is greater than the number of the calculators in the N×N convolution operation circuit.   
     
     
         6 . The neural network circuit according to  claim 1 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit and the number of the calculators in the N×N convolution operation circuit are n powers of 2, respectively.   
     
     
         7 . The neural network circuit according to  claim 1 , further comprising:
 a first weight memory that stores a weight coefficient used by the 1×1 convolution operation circuit; and   a second weight memory that stores a weight coefficient used by the N×N convolution operation circuit,   wherein the 1×1 convolution operation circuit and the N×N convolution operation circuit perform convolution operation in parallel.   
     
     
         8 . The neural network circuit according to  claim 1 ,
 wherein at least the 1×1 convolution operation circuit and the N×N convolution operation circuit are constructed on an FPGA.   
     
     
         9 . The neural network circuit according to  claim 8 ,
 wherein the SRAM is also constructed on the FPGA.   
     
     
         10 . The neural network circuit according to  claim 2 ,
 wherein N is 3.   
     
     
         11 . The neural network circuit according to  claim 2 ,
 wherein the number of calculators in the 1×1 convolution operation circuit and the number of calculators in the N×N convolution operation circuit are set according to a computation cost.   
     
     
         12 . The neural network circuit according to  claim 3 ,
 wherein the number of calculators in the 1×1 convolution operation circuit and the number of calculators in the N×N convolution operation circuit are set according to a computation cost.   
     
     
         13 . The neural network circuit according to  claim 2 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit and the number of the calculators in the N×N convolution operation circuit are n powers of 2, respectively.   
     
     
         14 . The neural network circuit according to  claim 3 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit and the number of the calculators in the N×N convolution operation circuit are n powers of  2 , respectively.   
     
     
         15 . The neural network circuit according to  claim 4 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit and the number of the calculators in the N×N convolution operation circuit are n powers of 2, respectively.   
     
     
         16 . The neural network circuit according to  claim 5 ,
 wherein the number of the calculators in the 1×1 convolution operation circuit and the number of the calculators in the N×N convolution operation circuit are n powers of 2, respectively.   
     
     
         17 . The neural network circuit according to  claim 2 , further comprising:
 a first weight memory that stores a weight coefficient used by the 1×1 convolution operation circuit; and   a second weight memory that stores a weight coefficient used by the N×N convolution operation circuit,   wherein the 1×1 convolution operation circuit and the N×N convolution operation circuit perform convolution operation in parallel.   
     
     
         18 . The neural network circuit according to  claim 3 , further comprising:
 a first weight memory that stores a weight coefficient used by the 1×1 convolution operation circuit; and   a second weight memory that stores a weight coefficient used by the N×N convolution operation circuit,   wherein the 1×1 convolution operation circuit and the N×N convolution operation circuit perform convolution operation in parallel.   
     
     
         19 . The neural network circuit according to  claim 4 , further comprising:
 a first weight memory that stores a weight coefficient used by the 1×1 convolution operation circuit; and   a second weight memory that stores a weight coefficient used by the N×N convolution operation circuit,   wherein the 1×1 convolution operation circuit and the N×N convolution operation circuit perform convolution operation in parallel.   
     
     
         20 . The neural network circuit according to  claim 5 , further comprising:
 a first weight memory that stores a weight coefficient used by the 1×1 convolution operation circuit; and   a second weight memory that stores a weight coefficient used by the N×N convolution operation circuit,   wherein the 1×1 convolution operation circuit and the N×N convolution operation circuit perform convolution operation in parallel.