Complementary depletion mode logic

Abstract

Disclosed is a semiconductor logic element including a field effect transistor of the first conductivity type and a field effect transistor of the second conductivity type. A gate of the first FET is an input of the semiconductor logic element, a drain of the second FET is referred to as the output of the semiconductor logic element and a source of the second FET is the source of the semiconductor logic element. By applying applicable potentials to the terminals of the field effect transistors it is possible to influence the state of the output of the logic element. Also disclosed are different kinds of logic circuitries including the described logic element.

1 . A semiconductor logic element comprising
 a depletion mode field effect transistor of the first conductivity type hereinafter referred to as a first FET comprising a first source, a first drain, a first gate, and a first channel, and   a depletion mode field effect transistor of the second conductivity type hereinafter referred to as a second FET comprising a second source, a second drain, a second gate, and a second channel;   wherein the semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the first drain and the second gate,   wherein the first gate is hereinafter referred to as an input of the semiconductor logic element, wherein the input is configured to be coupled either to a first input logic potential or to a second input logic potential,   wherein the second drain is referred to as an output of the semiconductor logic element,   wherein the second source is a source of the semiconductor logic element,   wherein the semiconductor logic element is configured so that when the first source is arranged at a first source potential and when the second source is at a first output logic potential and when the input is at the first input logic potential, then the first channel is arranged to be in a conductive stage and adjusting the internal node to the first source potential and thereby causing the second channel to be in a nonconductive state thus enabling the output of the semiconductor logic element to be either at the first output logic potential or at a second output logic potential, and   wherein the semiconductor logic element is further configured so that when the first source is arranged at the first source potential and when the second source is at the first output logic potential and when the input is at the second input logic potential, then the first channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the second channel to be in a conductive state thereby adjusting the output to the first output logic potential.   
     
     
         2 . The semiconductor logic element as claimed in  claim 1 , wherein the internal node comprises one of the following: a single doped region acting both as first drain and at least part of second gate, a first drain doping and a second gate. 
     
     
         3 . The semiconductor logic element as claimed in  claim 1 , wherein the first FET is one of the following: a junction field effect transistor, a conductor insulator semiconductor field effect transistor, a conductor semiconductor field effect transistor. 
     
     
         4 . The semiconductor logic element as claimed in  claim 1 , wherein the second FET is one of the following: a junction field effect transistor, a conductor insulator semiconductor field effect transistor, a conductor semiconductor field effect transistor. 
     
     
         5 . The semiconductor logic element as claimed in  claim 3 , wherein at least one of the following: the first FET, the second FET is a depletion mode conductor insulator semiconductor field effect transistor comprising an auxiliary gate corresponding to an external gate as well as a back-gate doping corresponding to a gate. 
     
     
         6 . The semiconductor logic element as claimed in  claim 5 , wherein
 if the first FET is a depletion mode conductor insulator semiconductor field effect transistor the auxiliary gate of the first FET is configured to be biased so that a layer of mobile second conductivity type charge carriers is established at the insulator semiconductor interface beneath the external gate of the first FET irrespective of whether the input is biased at the first input logic potential or at the second input logic potential, and the said layer of mobile second conductivity type charge carriers acting as a part of the first gate and controlling the first channel from the opposite side than the second conductivity type back-gate doping, and   if the second FET is a depletion mode conductor insulator semiconductor field effect transistor the auxiliary gate of the second FET is configured to be biased so that a layer of mobile first conductivity type charge carriers is established at the insulator semiconductor interface beneath the external gate of the second FET irrespective of whether the input is biased at the first input logic potential or at the second input logic potential, and the said layer of mobile first conductivity type charge carriers acting as a part of the second gate and controlling the second channel from the opposite side than the first conductivity type back-gate doping.   
     
     
         7 . The semiconductor logic element as claimed in  claim 3 , wherein
 if comprising a depletion mode conductor insulator semiconductor field effect transistor then the gate comprises both an external gate as well as a back-gate doping,   if comprising a depletion mode conductor semiconductor field effect transistor then the gate comprises both an external Schottky gate as well as a back-gate doping, and   if comprising a depletion mode junction field effect transistor having a front-gate doping and a back-gate doping then the gate comprises both the front-gate doping and the back-gate doping.   
     
     
         8 . The semiconductor logic element as claimed in  claim 3 , wherein
 if comprising a depletion mode conductor insulator semiconductor field effect transistor then the gate corresponds either to an external gate or to a back-gate doping and wherein the gate controls the channel only from the side where the gate is located,   if comprising a depletion mode conductor semiconductor field effect transistor then the gate corresponds either to an external Schottky gate or to a back-gate doping and wherein the gate controls the channel only from the side where the gate is located, and   if comprising a depletion mode junction field effect transistor having a front-gate doping and a back-gate doping then the gate corresponds either to the front-gate doping or to the back-gate doping and wherein the gate controls the channel only from the side where the gate is located.   
     
     
         9 . A first semiconductor logic element comprising
 a field effect transistor of the p type hereinafter referred to as the third FET comprising a third source, a third drain, a third gate, and a third channel, and   a field effect transistor of the n type hereinafter referred to as the fourth FET comprising a fourth source, a fourth drain, a fourth gate, and a fourth channel;   wherein the first semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the third drain and the fourth gate, wherein the third gate is hereinafter referred to as an input of the first semiconductor logic element, wherein the input is configured to be coupled either to a third input logic potential or to a fourth input logic potential, wherein the fourth drain is referred to as an output of the first semiconductor logic element,   wherein the fourth source is a source of the first semiconductor logic element,   wherein the first semiconductor logic element is configured so that when the third source is arranged at a third source potential and when the fourth source is at a third output logic potential and when the input is at the third input logic potential, then the third channel is arranged to be in a conductive stage adjusting the internal node to the third source potential and thereby causing the fourth channel to be in a nonconductive state thus enabling the output of the first semiconductor logic element to be either at the third output logic potential or at a fourth output logic potential, and   wherein the first semiconductor logic element is further configured so that when the third source is arranged at the third source potential and when the fourth source is at the third output logic potential and when the input is at the fourth input logic potential, then the third channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the fourth channel to be in a conductive state thereby adjusting the output to the third output logic potential.   
     
     
         10 . A second semiconductor logic element comprising
 a field effect transistor of the n type hereinafter referred to as the fifth FET comprising a fifth source, a fifth drain, a fifth gate, and a fifth channel, and   a field effect transistor of the p type hereinafter referred to as the sixth FET comprising a sixth source, a sixth drain, a sixth gate, and a sixth channel;   wherein the second semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the fifth drain and the sixth gate, wherein the fifth gate is hereinafter referred to as an input of the second semiconductor logic element, wherein the input is configured to be coupled either to a fifth input logic potential or to a sixth input logic potential,   wherein the sixth drain is referred to as an output of the second semiconductor logic element,   wherein the sixth source is a source of the second semiconductor logic element,   wherein the second semiconductor logic element is configured so that when the fifth source is arranged at a fifth source potential and when the sixth source is at a fifth output logic potential and when the input is at the fifth input logic potential, then the fifth channel is arranged to be in a conductive stage adjusting the internal node to the fifth source potential and thereby causing the sixth channel to be in a nonconductive state thus enabling the output of the second semiconductor logic element to be either at the fifth output logic potential or at a sixth output logic potential, and   wherein the second semiconductor logic element is further configured so that when the fifth source is arranged at the fifth source potential and when the sixth source is at the fifth output logic potential and when the input is at the sixth input logic potential, then the fifth channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the sixth channel to be in a conductive state thereby adjusting the output to the fifth output logic potential.   
     
     
         11 . A logic circuitry comprising at least one first semiconductor logic element as claimed in  claim 9  and at least one second semiconductor logic element, wherein each said at least one semiconductor logic element comprises:
 a field effect transistor of the n type hereinafter referred to as the fifth FET comprising a fifth source, a fifth drain, a fifth gate, and a fifth channel, and 
 a field effect transistor of the p type hereinafter referred to as the sixth FET comprising a sixth source, a sixth drain, a sixth gate, and a sixth channel; 
 wherein the second semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the fifth drain and the sixth gate, 
 wherein the fifth gate is hereinafter referred to as an input of the second semiconductor logic element, wherein the input is configured to be coupled either to a fifth input logic potential or to a sixth input logic potential, 
 wherein the sixth drain is referred to as an output of the second semiconductor logic element. wherein the sixth source is a source of the second semiconductor logic element, wherein the second semiconductor logic element is configured so that when the fifth source is arranged at a fifth source potential and when the sixth source is at a fifth output logic potential and when the input is at the fifth input logic potential, then the fifth channel is arranged to be in a conductive stage adjusting the internal node to the fifth source potential and thereby causing the sixth channel to be in a nonconductive state thus enabling the output of the second semiconductor logic element to be either at the fifth output logic potential or at a sixth output logic potential, and 
 wherein the second semiconductor logic element is further configured so that when the fifth source is arranged at the fifth source potential and when the sixth source is at the fifth output logic potential and when the input is at the sixth input logic potential, then the fifth channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the sixth channel to be in a conductive state thereby adjusting the output to the fifth output logic potential. 
 
     
     
         12 . A logic circuitry comprising:
 a first semiconductor logic element as claimed in  claim 9 , and   a second semiconductor logic element, wherein each said at least one semiconductor logic element comprises:   a field effect transistor of the n type hereinafter referred to as the fifth FET comprising a fifth source, a fifth drain, a fifth gate, and a fifth channel, and   a field effect transistor of the p type hereinafter referred to as the sixth FET comprising a sixth source, a sixth drain, a sixth gate, and a sixth channel;   wherein the second semiconductor logic element comprises an internal node wherein the internal node is at least partly formed with the fifth drain and the sixth gate,   wherein the fifth gate is hereinafter referred to as an input of the second semiconductor logic element, wherein the input is configured to be coupled either to a fifth input logic potential or to a sixth input logic potential,   wherein the sixth drain is referred to as an output of the second semiconductor logic element   wherein the sixth source is a source of the second semiconductor logic element, wherein the second semiconductor logic element is configured so that when the fifth source is arranged at a fifth source potential and when the sixth source is at a fifth output logic potential and when the input is at the fifth input logic potential, then the fifth channel is arranged to be in a conductive stage adjusting the internal node to the fifth source potential and thereby causing the sixth channel to be in a nonconductive state thus enabling the output of the second semiconductor logic element to be either at the fifth output logic potential or at a sixth output logic potential, and   wherein the second semiconductor logic element is further configured so that when the fifth source is arranged at the fifth source potential and when the sixth source is at the fifth output logic potential and when the input is at the sixth input logic potential, then the fifth channel is arranged to be in a nonconductive state enabling the internal node to adjust to a potential causing the sixth channel to be in a conductive state thereby adjusting the output to the fifth output logic potential, and   wherein:
 the fifth input logic potential of the second semiconductor logic element corresponds to the fourth input logic potential of the first semiconductor logic element, 
 the sixth input logic potential of the second semiconductor logic element corresponds to the third input logic potential of the first semiconductor logic element, 
 the fifth output logic potential of the second semiconductor logic element corresponds to the fourth output logic potential of the first semiconductor logic element, and 
 the sixth output logic potential of the second semiconductor logic element corresponds to the third output logic potential of the first semiconductor logic element. 
   
     
     
         13 . The logic circuitry as claimed in  claim 12 , wherein the logic circuit is configured to operate as an inverter configuration as follows:
 in the first semiconductor logic element the fourth source is connected to the third output logic potential of the first semiconductor logic element,   in the second semiconductor logic element the sixth source is connected to the fourth output logic potential of the first semiconductor logic element, wherein   the input of the first semiconductor logic element and the input of the second semiconductor logic element are connected together as an input of the inverter configuration,   the output of the first semiconductor logic element and the output of the second semiconductor logic element are connected together as an output of the inverter configuration, and   the input of the inverter configuration is configured to be coupled either to the third or the fourth input logic potential of the first semiconductor logic element wherein   when the input of the inverter configuration is coupled to the third input logic potential of the first semiconductor logic element the output of the inverter configuration sets to the fourth output logic potential of the first semiconductor logic element, and   when the input of the inverter configuration is coupled to the fourth input logic potential of the first semiconductor logic element the output of the inverter configuration sets to the third output logic potential of the first semiconductor logic element.   
     
     
         14 . The logic circuitry as claimed in  claim 12 , wherein the third input logic potential of the first semiconductor logic element is the same as the third output logic potential of the first semiconductor logic element and the fourth input logic potential of the first semiconductor logic element is the same as the fourth output logic potential of the first semiconductor logic element. 
     
     
         15 . A logic circuitry comprising at least one semiconductor logic element as claimed in  claim 1  and at least one complementary semiconductor logic element corresponding to a first conductivity type field effect transistor. 
     
     
         16 . A logic circuitry, wherein the logic circuit is configured to operate as an inverter configuration comprising:
 a semiconductor logic element as claimed in  claim 1 , and   a first conductivity type field effect transistor, the field effect transistor comprising:
 a first conductivity type source, 
 a first conductivity type drain, 
 a gate, and 
 a channel, 
   in the semiconductor logic element the second source is connected to the first output logic potential of the semiconductor logic element,   in the first conductivity type field effect transistor the source is connected to the second output logic potential of the semiconductor logic element, wherein   the drain of the field effect transistor and the output of the semiconductor logic element are connected together as an output of the inverter configuration, and   the gate of the field effect transistor and the input of the semiconductor logic element are connected together as an input of the inverter configuration;   the input of the inverter configuration is configured to be coupled either to the first or the second input logic potential of the semiconductor logic element, wherein   when the input of the inverter configuration is coupled to the first input logic potential of the semiconductor logic element, then the channel of the field effect transistor is arranged to be in a conductive state so that the output of the inverter configuration sets to the second output logic potential of the semiconductor logic element, and   when the input of the inverter configuration is coupled to the second input logic potential of the semiconductor logic element, the channel of the field effect transistor is nonconductive causing the output of the inverter configuration to the first output logic potential of the semiconductor logic element.   
     
     
         17 . The logic circuitry as claimed in  claim 16 , wherein the field effect transistor is one of the following: conductor insulator semiconductor field effect transistor, junction field effect transistor, conductor semiconductor field effect transistor. 
     
     
         18 . The logic circuitry as claimed in  claim 16 , wherein the first input logic potential of the semiconductor logic element is the same as the first output logic potential of the semiconductor logic element and the second input logic potential of the semiconductor logic element is the same as the second output logic potential of the semiconductor logic element. 
     
     
         19 . A multi-level logic circuitry comprising logic circuitries, including a first logic circuitry and a second logic circuitry as claimed in  claim 12 , wherein
 in the first logic circuitry at least one of the two output logic potentials of the first logic circuitry is shifted towards a first direction with respect to the two input logic potentials of the first logic circuitry,   in the second logic circuitry both input logic potentials are shifted towards the first direction with respect to the two input logic potentials of the first logic circuitry, and   at least one of the two output logic potentials of the second logic circuitry is shifted with respect to the two input logic potentials of the second logic circuitry towards the first direction.   
     
     
         20 . A multi-level logic circuitry comprising logic circuitries, including a first logic circuitry, a second logic circuitry and a third logic circuitry as claimed in  claim 12 , wherein
 in the first logic circuitry at least one of the two output logic potentials of the first logic circuitry is shifted towards a first direction with respect to the two input logic potentials of the first logic circuitry,   in the second logic circuitry both input logic potentials are shifted towards the first direction with respect to the two input logic potentials of the first logic circuitry,   at least one of the two output logic potentials of the second logic circuitry is shifted with respect to the two input logic potentials of the second logic circuitry towards the first direction,   in the third logic circuitry both input logic potentials are shifted towards the first direction with respect to the two input logic potentials of the second logic circuitry, and   at least one of the two output logic potential of the third logic circuitry is shifted with respect to the two input logic potentials of the third logic circuitry towards the first direction.