Semiconductor memory device and method for manufacturing same

Abstract

According to one embodiment, a method for manufacturing a semiconductor memory device includes forming a stacked body by alternately stacking an insulating film and a conductive film. The method includes forming a trench in the stacked body. The trench extends in one direction and divides the conductive film. The method includes burying a diblock copolymer in the trench. The method includes phase-separating the diblock copolymer into a plurality of first blocks and an insulative second block extending in a stacking direction of the insulating film and the conductive film. The method includes forming a plurality of holes by removing the first blocks. The method includes forming charge accumulation layers on inner surfaces of the holes. And, the method includes forming a plurality of semiconductor pillars extending in the stacking direction by burying a semiconductor material in the holes.

1 . (canceled) 
     
     
         2 . A semiconductor memory device, comprising:
 a stacked body including a plurality of insulating portions and a plurality of conductive films, each of the insulating portions and each of the conductive films being alternately stacked in a stacking direction above a substrate, trenches extending in the stacked body in a first direction intersecting with the stacking direction and dividing each of the conductive films in a second direction intersecting with the stacking direction and the first direction;   an underlying conductive layer provided between the substrate and the stacked body in the stacking direction;   a plurality of semiconductor pillars provided in the trenches and extending in the stacking direction, lower portions of a first semiconductor pillar and a second semiconductor pillar of the semiconductor pillars being coupled to the underlying conductive layer;   a plurality of insulating layers provided around the semiconductor pillars; and   an insulating member provided between the insulating layers around the semiconductor pillars in the trenches, the semiconductor pillars and the insulating member being alternately arranged in the first direction in the trenches,   a pair of memory transistors being provided so as to correspond to regions of each of the semiconductor pillars, the regions facing a pair of side surfaces of one of the trenches, the side surfaces extending along the first direction, the pair of memory transistors being disposed at an intersection between one of the semiconductor pillars and one of the conductive films, the pair of memory transistors being arranged in the second direction.   
     
     
         3 . The device according to  claim 2 , wherein each of the regions includes a plane parallel to the side surfaces of one of the trenches. 
     
     
         4 . The device according to  claim 2 , wherein each of the insulating layers includes a tunnel layer. 
     
     
         5 . The device according to  claim 2 , wherein each of the trenches has a first portion and second portions, a first dividing distance between divided parts of one of the conductive films at the first portion is shorter than a second dividing distance between the divided parts at the second portions, and the semiconductor pillars are located in the second portions. 
     
     
         6 . The device according to  claim 2 , wherein the trenches are arranged in the second direction, and the first semiconductor pillar is provided in a first one of the trenches and the second semiconductor pillar is provided in a second one of the trenches. 
     
     
         7 . The device according to  claim 2 , wherein the underlying conductive layer includes polysilicon. 
     
     
         8 . A semiconductor memory device, comprising:
 a stacked body including a plurality of conductive films stacked and insulated from each other in a stacking direction;   a plurality of first trenches extending in the stacked body in a first direction intersecting with the stacking direction and dividing each of the conductive films in a second direction intersecting with the stacking direction and the first direction;   a second trench extending in the stacking direction between the first trenches and being filled with an insulator;   a plurality of pillars provided in each of the first trenches and arranged spaced from each other in the first direction, each of the pillars including:
 a silicon channel extending in the stacking direction, and 
 an insulating layer provided on a first direction side and on a second direction side of the silicon channel; and 
   an insulating member provided between the pillars in the first trenches, the pillars and the insulating member being alternately arranged in the first direction in each of the first trenches, wherein   a pair of memory transistors are provided so as to correspond to regions of each of the pillars, the regions facing to one of the conductive films at both sides of the second direction.   
     
     
         9 . The device according to  claim 8 , wherein regions of side surfaces of the pillars include planes parallel to side surfaces of the first trenches, the side surfaces of the pillars facing to the side surfaces of the first trenches. 
     
     
         10 . The device according to  claim 8 , wherein neither any silicon channel nor any semiconductor pillar is provided in the second trench. 
     
     
         11 . The device according to  claim 8 , wherein the insulating layer includes a tunnel layer. 
     
     
         12 . The device according to  claim 8 , wherein the insulating member includes a portion having a length in the second direction shorter than a dividing distance in the second direction between divided parts of one of the conductive films via one of the first trenches at places where the pillars are located. 
     
     
         13 . The device according to  claim 8 , wherein each of the pillars includes an outer edge consisting of a pair of first sides including circular arcs and a pair of second sides of line segments as viewed in the stacking direction. 
     
     
         14 . The device according to  claim 8 , further comprising:
 a charge accumulation layer provided between the insulating layer and one of the conductive films; and   a block layer provided between the charge accumulation layer and the one of the conductive films,   the insulating layer being a tunnel layer.   
     
     
         15 . The device according to  claim 14 , wherein
 the tunnel layer includes silicon and oxygen,   the charge accumulation layer includes silicon, and   the block layer includes silicon and oxygen.   
     
     
         16 . A method for manufacturing a semiconductor memory device according to  claim 2 , the method comprising:
 forming the stacked body above the underlying conductive layer by alternately stacking a plurality of first films and a plurality of second films;   forming the trenches in the stacked body, the trenches extending in a first direction and dividing the stacked body in a second direction, the second direction intersecting with the first direction and a stacking direction of the first films and the second films;   burying the insulating member in the trenches;   forming a plurality of holes by removing selectively the insulating member, the holes being spaced from each other in the first direction in each of the trenches; and   forming the plurality of semiconductor pillars extending in the stacking direction in the holes via the insulating layers.   
     
     
         17 . The method according to  claim 16 , further comprising setting back side surfaces of the holes by etching after forming the holes. 
     
     
         18 . The method according to  claim 16 , wherein one of the semiconductor pillars is formed in one of the holes via a charge accumulation layer. 
     
     
         19 . The method according to  claim 16 , wherein one of the semiconductor pillars is formed in one of the holes via a block layer, a charge accumulation layer, and a tunnel layer, each of the insulating layers being a tunnel layer. 
     
     
         20 . The method according to  claim 16 , wherein
 a length of each of the trenches in the first direction is made longer than a length of each of the trenches in the second direction.   
     
     
         21 . The method according to  claim 16 , further comprising dividing the stacked body in the second direction at a position differing from the trenches.