High Voltage ESD Protection Apparatus

Abstract

A device comprises a high voltage n well and a high voltage p well over a buried layer, a first low voltage n well over the high voltage n well, wherein a bottom portion of the first low voltage n well is surrounded by the high voltage n well, an N+ region over the first low voltage n well, a second low voltage n well and a low voltage p well over the high voltage p well, a first P+ region over the second low voltage n well and a second P+ region over the low voltage p well.

What is claimed is: 
     
         1 . A semiconductor device comprising:
 a substrate;   a transistor in the substrate, comprising:
 a collector comprising an n-type region; 
 a base comprising a first p-type region; and 
 an emitter comprising an N well; 
   a first P well in the substrate and under the first p-type region;   a second P well in the substrate, wherein the first P well and the N well extend into the second P well;   a first isolation region in the substrate between the n-type region and the first p-type region;   a second isolation region in the substrate between the n-type region and the N well; and   a PN junction connected in series with the transistor, wherein the PN junction comprises the N well and a second p-type region over the N well.   
     
     
         2 . The semiconductor device of  claim 1 , wherein the second p-type region is a p-type metal contact. 
     
     
         3 . The semiconductor device of  claim 2 , wherein a lower surface of the p-type metal contact facing the substrate contacts and extends along an upper surface of the N well. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the n-type region, the first p-type region, the N well, the first isolation region, and the second isolation region have a coplanar upper surface. 
     
     
         5 . The semiconductor device of  claim 4 , wherein the first isolation region extends continuously from the first p-type region to the n-type region, and wherein the second isolation region extends continuously from the n-type region to the N well. 
     
     
         6 . The semiconductor device of  claim 5 , wherein the first isolation region and the second isolation region extend deeper into the substrate than the n-type region and the first p-type region, wherein the N well extends deeper into the substrate than the first isolation region and the second isolation region. 
     
     
         7 . The semiconductor device of  claim 1 , wherein the first P well contacts and extends along a lower surface of the first p-type region. 
     
     
         8 . The semiconductor device of  claim 7 , wherein the first P well further contacts and extends along a sidewall of the first isolation region and a first portion of a bottom surface of the first isolation region. 
     
     
         9 . The semiconductor device of  claim 8 , wherein the second P well contacts and extends along a second portion of the bottom surface of the first isolation region. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the N well contacts and extends along a sidewall of the second isolation region and a first portion of a bottom surface of the second isolation region, wherein the second P well contacts and extends along a second portion of the bottom surface of the second isolation region. 
     
     
         11 . The semiconductor device of  claim 10 , wherein the second P well contacts and extends along a lower surface of the n-type region, wherein there is a depletion region at the lower surface of the n-type region. 
     
     
         12 . A semiconductor device comprising:
 a substrate;   a diode having a PN junction, the diode comprising a metal contact and an N well, wherein the N well is in the substrate, and the metal contact is over the N well;   a transistor in the substrate and connected in series with the diode, wherein the transistor comprises an emitter, a collector, and a base, wherein the collector comprises an n-type region, the base comprises a p-type region, and the emitter comprises the N well;   a first P well in the substrate and under the p-type region; and   a second P well in the substrate, wherein the second P well extends along a lower surface of the n-type region, and at least partially surrounds the first P well and the N well.   
     
     
         13 . The semiconductor device of  claim 12 , wherein the metal contact is a p-type metal contact. 
     
     
         14 . The semiconductor device of  claim 12 , wherein the n-type region is in the substrate and laterally between the N well and the p-type region. 
     
     
         15 . The semiconductor device of  claim 14 , further comprises:
 a first isolation region in the substrate and extending continuously from the p-type region to the n-type region; and   a second isolation region in the substrate and extending continuously from the n-type region to the N well.   
     
     
         16 . The semiconductor device of  claim 15 , wherein the first P well contacts and extends along the p-type region and a first portion of a bottom surface of the first isolation region, wherein the N well contacts and extends along a first portion of a bottom surface of the second isolation region, wherein the second P well contacts and extends along a second portion of the bottom surface of the first isolation region and a second portion of the bottom surface of the second isolation region. 
     
     
         17 . A semiconductor device comprising:
 a substrate;   a transistor in the substrate, the transistor comprising:
 a base; 
 an emitter; and 
 a collector, wherein the collector is disposed in the substrate laterally between the base and the emitter; 
   a first isolation region in the substrate between the base and the collector;   a second isolation region in the substrate between the emitter and the collector;   a third isolation region in the substrate, wherein the emitter is between the second isolation region and the third isolation region; and   a diode connected in series with the transistor, the diode comprising a metal contact forming a PN junction with the emitter of the transistor, wherein the metal contact overlies the emitter and extends continuously from the second isolation region to the third isolation region.   
     
     
         18 . The semiconductor device of  claim 17 , wherein the base is a first doped semiconductor region in the substrate, the collector is a second doped semiconductor region in the substrate, and the emitter is a first well region in the substrate. 
     
     
         19 . The semiconductor device of  claim 18 , further comprising:
 a second well region in the substrate under the first doped semiconductor region; and   a third well region in the substrate, wherein the first well region and the second well region extend into the third well region, wherein the first well region has a first dopant of a first type, the first type being n-type or p-type, wherein the second well region and the third well region has a second dopant of a second type different from the first type, the second type being p-type or n-type.   
     
     
         20 . The semiconductor device of  claim 19 , wherein the first well region covers a first portion of a lower surface of the second isolation region, and the second well region covers a first portion of a lower surface of the first isolation region, wherein the third well region covers a second portion of the lower surface of the first isolation region and a second portion of the lower surface of the second isolation region.