Double-pitch-layout techniques and apparatus thereof

Abstract

Examples pertaining to double-pitch layout techniques in designing a memory circuit layout are described. In a memory circuit, a layout of a first column of M×1 one-bit memory cells of an array of memory cells and a layout of a second column of M×1 one-bit memory cells of the array of memory cells are mirrored in horizontal and vertical axes such that a first group of input/output (I/O) pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of a layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array.

1 . An apparatus, comprising:
 a substrate; and   a memory circuit on the substrate, the memory circuit comprising an array of memory cells, control circuits, a word-line driver, and a plurality of input/output (I/O) circuits, the plurality of I/O circuits comprising a plurality of I/O pins comprising at least a first group of I/O pins and a second group of I/O pins, wherein:   an M×N array of one-bit memory cells of the array of memory cells are grouped into N/2 two-column pairs of M×1 one-bit memory cells with respective I/O circuits of the plurality of I/O circuits, with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns,   each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells and a second column of M×1 one-bit memory cells,   a layout of the first column of M×1 one-bit memory cells and a layout of the second column of M×1 one-bit memory cells is such that the first group of I/O pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of the layout of the array and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side opposite the first side of the layout of the array,   wherein the plurality of I/O circuits includes a first I/O circuit comprising a sense amplifier, wherein the first I/O circuit is coupled to a single column of M×1 one-bit memory cells.   
     
     
         2 . The apparatus of  claim 1 , wherein, wherein the plurality of I/O circuits comprise I/O pins comprising data-in (DI) pins, data-out (DO) pins, and BYTE pins, and wherein pitches of the I/O pins are equal to twice of a pitch of each of the one-bit memory cells. 
     
     
         3 . The apparatus of  claim 1 , wherein the plurality I/O circuits of the two-column memory cell are located on the first side and the second side of the layout. 
     
     
         4 . The apparatus of  claim 1 , wherein the plurality of I/O circuits each comprises a pre-charging circuitry and a sense amplifier (SA). 
     
     
         5 . The apparatus of  claim 1 , wherein the memory circuit further comprises an additional control circuit that functions as a global signal buffer. 
     
     
         6 . The apparatus of  claim 1 , wherein the memory circuit further comprises power switches located on the first side of the layout and the second side of the layout, and wherein the power switches control a power bias of the memory circuit. 
     
     
         7 . The apparatus of  claim 1 , wherein the memory circuit further comprises an internal power mesh, and wherein a pitch of the internal power mesh is four times a pitch of corresponding I/O pins of each of the one-bit memory cells. 
     
     
         8 . The apparatus of  claim 1 , wherein layouts of the M×N array of one-bit memory cells and the plurality of I/O circuits are grouped into N/4 of four-column groups of M×1 memory cells, wherein:
 each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells, a second column of M×1 one-bit memory cells, a third column of M×1 one-bit memory cells, and a fourth column of M×1 one-bit memory cells, 
 layouts of the first column, second column, third column and fourth column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that a first set of I/O pins corresponding to the first column of M×1 one-bit memory cells and a third set of I/O pins corresponding to the third column of M×1 one-bit memory cells are on the first side of the layout of the array, and a second set of I/O pins corresponding to the second column of M×1 one-bit memory cells and a fourth set of I/O pins corresponding to the fourth column of M×1 one-bit memory cells are on the second side of the layout of the array. 
 
     
     
         9 . The apparatus of  claim 1 , wherein layouts of the M×N array of one-bit memory cells and the I/O circuits are grouped into N/P of P columns of M×1 one-bit memory cells, with P being a positive integer, wherein:
 layouts of the P columns of M×1 one-bit memory cells are mirrored in horizontal and vertical axes such that the first group of I/O pins are on the first side of the layout of the array and the second group of I/O pins are on the second side of the layout of the array. 
 
     
     
         10 . An apparatus, comprising:
 a memory circuit comprising a plurality of input/output (I/O) circuits and an array of memory cells, the array of memory cells comprising an M×N array of one-bit memory cells, with M being a positive integer representative of a number of rows and N being a positive integer representative of a number of columns, wherein:   the M×N array of one-bit memory cells are grouped into N/2 two-column pairs of M×1 one-bit memory cells, and   each of the two-column pairs of M×1 memory cells comprises a first column of M×1 one-bit memory cells and a second column of M×1 one-bit memory cells such that a layout of the first column of M×1 one-bit memory cells and a layout of the second column of M×1 one-bit memory cells are mirrored in horizontal and vertical axes,   wherein the plurality of I/O circuits includes a first I/O circuit comprising a sense amplifier, wherein the first I/O circuit is coupled to a single column of M×1 one-bit memory cells.   
     
     
         11 . The apparatus of  claim 10 , further comprising:
 a first group of input/output (I/O) pins; and   a second group of I/O pins,   wherein, for each of the two-column pairs of M×1 memory cells, the first group of I/O pins, which correspond to the first column of M×1 one-bit memory cells, are on a first side of the layout of the array of memory cells and the second group of I/O pins, which correspond to the second column of M×1 one-bit memory cells, are on a second side of the layout of the array opposite the first side thereof.