Cross-threaded memory system

Abstract

A multi-chip package includes a logic integrated circuit (IC) die formed with plural memory controller circuits, a first memory IC die and a second memory IC die. The second memory IC die is mounted to the first memory IC die. The first memory IC die and the logic IC die are mounted to one another. The logic IC die includes a serial link interface for coupling to multiple serial links. The first memory die includes a first memory group accessed by a first one of the plural memory controller circuits, and a second memory group accessed by a second one of the plural memory controller circuits.

1 . (canceled) 
     
     
         2 . An integrated circuit (IC) chip, comprising:
 control interface circuitry for coupling to multiple memory access requestors;   memory interface circuitry for coupling to multiple groups of memory resources; and   switching circuitry to switchably interconnect the multiple memory access requestors to the multiple groups of memory resources.   
     
     
         3 . The IC chip of  claim 2 , wherein:
 the switching circuitry, within a first time interval, is to couple any one of the memory access requestors via the control interface circuitry exclusively to any of the multiple groups of memory resources via the memory interface circuitry.   
     
     
         4 . The IC chip of  claim 3 , wherein:
 the switching circuitry, within a second time interval that at least partially overlaps with the first time interval, is to couple each of the other memory access requestors via the control interface circuitry exclusively to another of the multiple groups of memory resources via the memory interface circuitry.   
     
     
         5 . The IC chip of  claim 2 , wherein the switching circuitry comprises:
 crossbar switching circuitry.   
     
     
         6 . The IC chip of  claim 2 , wherein the memory interface circuitry includes:
 at least one command/address (C/A) transfer circuit.   
     
     
         7 . The IC chip of  claim 2 , wherein the memory interface circuitry includes:
 at least one data transfer circuit.   
     
     
         8 . The IC chip of  claim 2 , wherein:
 the memory interface circuitry is to communicate with the multiple groups of memory resources via a dynamic random access memory (DRAM) protocol.   
     
     
         9 . The IC chip of  claim 2 , realized as a buffer IC chip to buffer signals transferred between the multiple memory access requestors and the multiple groups of memory resources. 
     
     
         10 . An integrated circuit (IC) buffer device to buffer signals transferred between multiple memory access requestors and multiple groups of memory resources, the IC buffer device comprising:
 a primary interface for coupling to the multiple memory access requestors;   a secondary interface for coupling to the multiple groups of memory devices; and   crossbar switching circuitry to switchably interconnect a selected one of the multiple memory access requestors to a selected one of the multiple groups of memory resources.   
     
     
         11 . The IC buffer device of  claim 10 , wherein:
 the crossbar switching circuitry is to switchably interconnect a primary data path associated with the selected one of the multiple memory access requestors to a secondary data path associated with the selected one of the multiple groups of memory resources.   
     
     
         12 . The IC buffer device of  claim 11 , realized as an IC data buffer device. 
     
     
         13 . The IC buffer device of  claim 10 , wherein:
 the crossbar switching circuitry is to switchably interconnect a primary command/address (C/A) path associated with the selected one of the multiple memory access requestors to a secondary C/A path associated with the selected one of the multiple groups of memory resources.   
     
     
         14 . The IC buffer device of  claim 13 , realized as an IC address buffer device. 
     
     
         15 . The IC buffer device of  claim 10 , wherein:
 the crossbar switching circuitry, within a first time interval, is to couple any one of the memory access requestors via the control interface circuitry exclusively to any of the multiple groups of memory resources via the memory interface circuitry.   
     
     
         16 . The IC buffer device of  claim 10 , wherein:
 the crossbar switching circuitry, within a second time interval that at least partially overlaps with the first time interval, is to couple each of the other memory access requestors via the control interface circuitry exclusively to another of the multiple groups of memory resources via the memory interface circuitry.   
     
     
         17 . A method of operating an integrated circuit (IC) buffer chip, comprising:
 buffering signals transferred between multiple memory access requestors and multiple groups of memory resources, the buffering signals including:
 coupling the multiple memory access requestors to a primary interface of the IC buffer chip; 
 coupling the multiple groups of memory resources to a secondary interface of the IC buffer chip; and 
 switchably interconnecting a selected one of the multiple memory access requestors to a selected one of the multiple groups of memory resources via a crossbar switch. 
   
     
     
         18 . The method of  claim 17 , wherein the switchably interconnecting comprises:
 switchably interconnecting a primary data path associated with the selected one of the multiple memory access requestors to a secondary data path associated with the selected one of the multiple groups of memory resources.   
     
     
         19 . The method of  claim 17 , wherein the switchably interconnecting comprises:
 switchably interconnecting a primary command/address (C/A) path associated with the selected one of the multiple memory access requestors to a secondary C/A path associated with the selected one of the multiple groups of memory resources.   
     
     
         20 . The method of  claim 17 , wherein the switchably interconnecting comprises:
 within a first time interval, coupling any one of the memory access requestors via the primary interface exclusively to any of the multiple groups of memory resources via the secondary interface.   
     
     
         21 . The method of  claim 17 , wherein the switchably interconnecting comprises:
 within a second time interval that at least partially overlaps with the first time interval, coupling each of the other memory access requestors via the primary interface exclusively to another of the multiple groups of memory resources via the secondary interface.