System and Method for Shared Memory Ownership Using Context

Abstract

It is possible to reduce the latency attributable to memory protection in shared memory systems by performing access protection at a central Data Ownership Manager (DOM), rather than at distributed memory management units in the central processing unit (CPU) elements (CEs) responsible for parallel thread processing. In particular, the DOM may monitor read requests communicated over a data plane between the CEs and a memory controller, and perform access protection verification in parallel with the memory controller's generation of the data response. The DOM may be separate and distinct from both the CEs and the memory controller, and therefore may generally be able to make the access determination without interfering with data plane processing/generation of the read requests and data responses exchanged between the memory controller and the CEs.

What is claimed is: 
     
         1 . An apparatus comprising:
 a data plane;   a memory controller coupled to the data plane;   a plurality of central processing unit (CPU) elements (CEs) coupled to the data plane, the plurality of CEs including a CE configured to send a read request to the memory controller over the data plane, the read request requesting access to a shared memory resource; and   a Data Ownership Manager (DOM) coupled to the data plane, the DOM being configured to detect the read request, to determine whether a thread assigned to the CE is permitted to access the shared memory resource based on one or more identifiers (IDs) in the read request, and to send a control signal to the memory controller indicating whether the thread being executed by the CE is permitted to access the shared memory resource.