Semiconductor device and method for fabricating the same

Abstract

A method for fabricating a semiconductor device includes: forming a lower array including a plurality of bottom electrodes over a semiconductor substrate, a supporter supporting the bottom electrodes, and a dielectric layer that is formed over the bottom electrodes and the supporter; forming a gap-fill layer covering side portions of the lower array and an upper portion of the lower array; forming a capping portion covering the upper portion of the lower array over the gap-fill layer; performing a pull-back process of the gap-fill layer to form a gap-fill electrode aligned with the capping portion; and forming a low-resistivity electrode over the gap-fill electrode.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a peripheral circuit region including a lower level interconnection;   a contact plug coupled to the lower level interconnection; and   a memory cell region including a multi-level supporter laterally spaced apart from the contact plug, bottom electrodes supported by the multi-level supporter, and a top electrode filling a space between the bottom electrodes,   wherein the top electrode includes:
 a liner electrode that conformally covers the bottom electrodes and the supporter; and 
 a gap-fill electrode including a gap-fill electrode upper portion which is positioned at a higher level than the bottom electrodes to cover the bottom electrodes and the multi-level supporter over the liner electrode, and supporter-side side portions which are thinner than the gap-fill electrode upper portion and covering an edge portion of the multi-level supporter. 
   
     
     
         2 . The semiconductor device of  claim 1 , wherein the supporter-side side portions of the gap-fill electrode cover the edge portion of the multi-level supporter at an edge portion of the memory cell region. 
     
     
         3 . The semiconductor device of  claim 1 , wherein the supporter-side side portions of the gap-fill electrode have a vertical profile. 
     
     
         4 . The semiconductor device of  claim 1 , wherein the gap-fill electrode further includes:
 bottom electrode-side side portions that extend from the supporter-side side portions,   wherein the bottom electrode-side side portions are thicker than the supporter-side side portions.   
     
     
         5 . The semiconductor device of  claim 1 , wherein the gap-fill electrode includes a silicon layer, a boron-doped silicon layer, a silicon germanium layer, a boron-doped silicon germanium layer, silicon carbide, or a combination thereof. 
     
     
         6 . The semiconductor device of  claim 1 , wherein the top electrode further includes:
 a low-resistivity electrode including:
 a low-resistivity electrode upper portion covering the gap-fill electrode upper portion; and 
 low-resistivity electrode side portions covering the supporter-side side portions. 
   
     
     
         7 . The semiconductor device of  claim 6 , wherein the gap-fill electrode further includes a lateral edge portion that extends from the supporter-side side portions to be defined in a bottom portion of an edge portion of the memory cell region, and
 an end of the lateral edge portion and the low-resistivity electrode side portions are self-aligned.   
     
     
         8 . The semiconductor device of  claim 6 , wherein the low-resistivity electrode side portions fully cover the supporter-side side portions. 
     
     
         9 . The semiconductor device of  claim 6 , wherein the gap-fill electrode is embedded between the low-resistivity electrode and the liner electrode. 
     
     
         10 . The semiconductor device of  claim 1 , wherein the gap-fill electrode covers side portions and upper portion of the memory cell region while filling a space between the bottom electrodes, and
 the low-resistivity electrode covers the side portions and the upper portion of the memory cell region while not filling the space between the bottom electrodes.