Semiconductor memory and nonvolatile memory

Abstract

According to one embodiment, a semiconductor memory includes: a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states; a word line coupled to the plurality of memory cells; and a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein a first page size of page data of the memory group is smaller than a second page

What is claimed is: 
     
         1 . A semiconductor memory comprising:
 a memory group including a plurality of memory cells configured to store a plurality of bits of data in three or more plurality of states;   a word line coupled to the plurality of memory cells; and   a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein   a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address.   
     
     
         2 . The semiconductor memory according to  claim 1 , wherein the input data is written in at least two bits of a part of the plurality of memory cells. 
     
     
         3 . The semiconductor memory according to  claim 1 , wherein, when
 the second page size is described as “m”,   the number of pages of the input data included in an order received from the external controller is described as “a”,   the number of pages of the page data of the memory group is described as “b”, and   the first page size is described as “n”,   n=m×a/b is established.   
     
     
         4 . The semiconductor memory according to  claim 1 , wherein, in a read operation, a plurality of pages of the page data are read from the memory group, and at least a part of the plurality of pages of the page data is combined and output. 
     
     
         5 . The semiconductor memory according to  claim 1 , wherein at least one bit of the plurality of bits of the plurality of memory cells is determined by one read operation using one read voltage. 
     
     
         6 . A semiconductor memory comprising:
 a memory group including a plurality of first memory cells and a plurality of second memory cells;   a word line coupled to the plurality of first memory cells and the plurality of second memory cells; and   a first circuit configured to convert one external address received from an external controller into a plurality of internal addresses, wherein   a first page size of page data of the memory group is smaller than a second page size of input data corresponding to the external address, and   a set of one of the plurality of first memory cells and one of the plurality of second memory cells is configured to store a plurality of bits of data.   
     
     
         7 . The semiconductor memory according to  claim 6 , wherein, when
 the second page size is described as “m”,   the number of pages of the input data included in an order received from the external controller is described as “a”,   the number of bits of data that is being capable of storing in the set is described as “c”, and   the first page size is described as “n”,   n=m×2 a/c is established.   
     
     
         8 . A nonvolatile memory comprising:
 a plurality of memory cells configured to store three bits of data described by first to third bits and allocated to eight threshold areas that include a first threshold area indicating an erase area and second to eighth threshold areas each indicating write areas, the threshold voltages of the the second to eighth threshold areas being higher than a threshold voltage of the first threshold area, the g-th threshold area (g is a natural number from two to eight) indicating one of the second to eighth threshold areas having a higher threshold voltage than the (g−1)-th threshold area;   a word line coupled to the plurality of memory cells; and   a controller configured to execute a read operation with respect to the plurality of memory cells in response to a read command from an external controller, wherein   among first to seventh voltages existing between adjacent threshold areas of the first to eighth threshold areas, the number of voltages used for determining a value of data of the first bit is one, the number of voltages used for determining a value of data of the second bit is p (p is a natural number from two to four), and the number of voltages used for determining a value of data of the third bit is (6−p),   an address specified by the read command corresponds to one of a first page address and a second page address,   in a case where the specified address corresponds to the first page address, the controller is configured to read data from the plurality of memory cells by using a voltage used for determining the value of data of the first bit and the p voltages used for determining the value of data of the second bit among the first to seventh voltages, and   in a case where the specified address corresponds to the second page address, the controller is configured to read data from the plurality of memory cells by using a voltage used for determining the value of data of the first bit and the (6−p) voltages used for determining the value of data of the third bit among the first to seventh voltages.   
     
     
         9 . The nonvolatile memory according to  claim 8 , wherein the h-th voltage (h is a natural number from two to seven) is higher than the (h−1)-th voltage, and the fourth voltage is the voltage used for determining the value of data of the first bit. 
     
     
         10 . The nonvolatile memory according to  claim 9 , wherein the p is three. 
     
     
         11 . The nonvolatile memory according to  claim 10 , wherein
 the first voltage, the third voltage, and the sixth voltage are used for determining the value of data of the second bit, and   the second voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the third bit.   
     
     
         12 . The nonvolatile memory according to  claim 9 , wherein the p is four. 
     
     
         13 . The nonvolatile memory according to  claim 12 , wherein
 the first voltage, the third voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the second bit, and   the second voltage and the sixth voltage are used for determining the value of data of the third bit.   
     
     
         14 . The nonvolatile memory according to  claim 9 , wherein the p is two. 
     
     
         15 . The nonvolatile memory according to  claim 14 , wherein
 the second voltage and the sixth voltage are used for determining the value of data of the second bit, and   the first voltage, the third voltage, the fifth voltage, and the seventh voltage are used for determining the value of data of the third bit.