Magnetoresistive devices and methods of fabricating such devices

Abstract

An integrated circuit (IC) device includes a logic portion including logic circuits in multiple vertically stacked metal layers interconnected by one or more via layers, and a memory portion with a plurality of magnetoresistive devices. Each magnetoresistive device is provided in a single metal layer of the multiple vertically stacked metal layers of the IC device.

1 - 20 . (canceled) 
     
     
         21 . An integrated circuit device comprising:
 a plurality of vertically stacked metal layers, including a first metal layer and a second metal layer;   a plurality of via layers, including a first via layer between the first metal layer and the second metal layer;   a logic portion comprising logic circuits including the first metal layer, the second metal layer, and the first via layer;   a memory portion including the first metal layer, the second metal layer, and the first via layer; and   a plurality of magnetoresistive devices, wherein each magnetoresistive device of the plurality of magnetoresistive devices is provided in the first metal layer or the second metal layer of the memory portion.   
     
     
         22 . The device of  claim 21 , wherein a via within the logic portion of the first via layer has substantially the same height as a via within the memory portion of the first via layer. 
     
     
         23 . The device of  claim 21 , wherein the plurality of via layers further includes a second via layer;
 the second metal layer is between the first via layer and the second via layer;   the logic circuits further include the second via layer; and   the memory portion further includes the second via layer   
     
     
         24 . The device of  claim 23 , wherein a combined height of a via within the memory portion of the second via layer and a magnetoresistive device of the plurality of magnetoresistive devices is substantially the same as a combined height of a feature of the logic circuits within the second metal layer and a via within the logic portion of the second via layer. 
     
     
         25 . The device of  claim 23 , wherein a via within the logic portion of the second via layer has substantially the same height as a via within the memory portion of the second via layer. 
     
     
         26 . The device of  claim 25 , wherein each magnetoresistive device of the plurality of magnetoresistive devices is provided in the second metal layer of the memory portion. 
     
     
         27 . The device of  claim 26 , wherein each magnetoresistive device of the plurality of magnetoresistive devices lands on a corresponding via within the memory portion of the first via layer, and each magnetoresistive device has a width greater than a width of the corresponding via. 
     
     
         28 . The device of  claim 26 , wherein a magnetoresistive device of the plurality of magnetoresistive devices has a height that is substantially the same as a height of a feature of the logic circuits within the second metal layer. 
     
     
         29 . An integrated circuit device comprising:
 a plurality of vertically stacked metal layers, including a first metal layer;   a plurality of via layers, including a first via layer and a second via layer, wherein the first metal layer is between the first via layer and the second via layer;   a logic portion comprising logic circuits including the first metal layer, the first via layer, and the second via layer;   a memory portion including the first metal layer, the first via layer, and the second via layer; and   a plurality of magnetoresistive devices, wherein each magnetoresistive device of the plurality of magnetoresistive devices is within the memory portion and between the first via layer and the second via layer;   wherein a combined height of a magnetically free region, a magnetically fixed region, and an intermediate region of at least one magnetoresistive device of the plurality of magnetoresistive devices, is less than or equal to a height of the first metal layer.   
     
     
         30 . The device of  claim 29 , wherein a feature of the logic circuits within the first metal layer has a height that is substantially the same as a height of the at least one magnetoresistive device of the plurality of magnetoresistive devices. 
     
     
         31 . The device of  claim 29 , further comprising a second metal layer, wherein the logic circuits further include the second metal layer; and
 vias within the logic portion of the second via layer, connect the first metal layer to the second metal layer.   
     
     
         32 . The device of  claim 31 , wherein the memory portion further includes the second metal layer; and
 wherein a height of a via within the memory portion of the second via layer is substantially the same as a height of a via within the logic portion of the second via layer.   
     
     
         33 . The device of  claim 32 , further comprising:
 a third metal layer; and   a third via layer between the first metal layer and the third metal layer;   where the logic circuits further include the third metal layer and the third via layer; and   the memory portion further includes the third metal layer and the third via layer.   
     
     
         34 . The device of  claim 33 , wherein a width of the at least one magnetoresistive device is less than a width of a via within the memory portion of the third via layer. 
     
     
         35 . The device of  claim 33 , wherein a height of a via within a memory portion of the third via layer is substantially the same as a height of a via within the third via layer of the logic circuits. 
     
     
         36 . An integrated circuit device comprising:
 a plurality of vertically stacked metal layers, including a first metal layer;   a plurality of via layers, including a first via layer and a second via layer, wherein the first metal layer is between the first via layer and the second via layer;   a logic portion comprising logic circuits including the first metal layer, the first via layer, and the second via layer;   a memory portion including the first metal layer, the first via layer, and the second via layer; and   a plurality of magnetoresistive devices, wherein each magnetoresistive device of the plurality of magnetoresistive devices is provided in the first metal layer; and   wherein a via within the logic portion of the first via layer has substantially the same height as a via within the memory portion of the first via layer.   
     
     
         37 . The device of  claim 36 , wherein a via within the logic portion of the second via layer has substantially the same height as a via within the memory portion of the second via layer. 
     
     
         38 . The device of  claim 36 , wherein at least one magnetoresistive device of the plurality of magnetoresistive devices includes a synthetic antiferromagnetic structure, a synthetic ferromagnetic structure, or both. 
     
     
         39 . The device of  claim 36 , wherein a height of the first via layer is at least about one-third of a height of the first metal layer. 
     
     
         40 . The device of  claim 36 , wherein a height of the first metal layer is greater than a combined height of the first via layer and the second via layer.