Solid-state image-capturing element and electronic device

Abstract

Provided are a solid-state image-capturing element and an electronic device capable of reducing the capacitance by using a hollow region. At least a part of a region between an FD wiring connected to a floating diffusion and a wiring other than the FD wiring is a hollow region. The present disclosure can be applied to a CMOS image sensor having, for example, a floating diffusion, a transfer transistor, an amplifying transistor, a selection transistor, a reset transistor, and a photodiode.

What is claimed is: 
     
         1 . A semiconductor device, comprising:
 a first silicon layer;   a second silicon layer bonded to the first silicon layer; and   a wiring layer configured to electrically connect the first silicon layer to the second silicon layer, wherein a first hollow region is around the wiring layer.   
     
     
         2 . The semiconductor device according to  claim 1 , wherein the wiring layer includes:
 a first insulating film including a first material, and   a second insulting film including a second material different from the first material.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein
 a second hollow region is around the wiring layer, and   the first insulating film is between the first hollow region and the second hollow region.   
     
     
         4 . The semiconductor device according to  claim 1 , wherein the first silicon layer includes a floating diffusion. 
     
     
         5 . The semiconductor device according to  claim 4 , wherein
 the wiring layer includes:
 a second hollow region, 
 a third hollow region, and 
 a wiring connected to the floating diffusion, and 
   the wiring is between the second hollow region and the third hollow region in a first direction.   
     
     
         6 . The semiconductor device according to  claim 5 , wherein the wiring is not in contact with each of the first hollow region, the second hollow region, and the third hollow region. 
     
     
         7 . The semiconductor device according to  claim 5 , wherein
 the wiring layer further includes a transfer transistor, and   the transfer transistor is between the second hollow region and the first silicon layer in a second direction perpendicular to the first direction.