Semiconductor device including an antenna

Abstract

A semiconductor device includes a semiconductor chip and a redistribution layer on a first side of the semiconductor chip. The redistribution layer is electrically coupled to the semiconductor chip. The semiconductor device includes a dielectric layer and an antenna on the dielectric layer. The dielectric layer is between the antenna and the semiconductor chip.

1 . A semiconductor device comprising:
 a semiconductor chip having a first side and a second side;   a redistribution layer on the first side of the semiconductor chip, the redistribution layer electrically coupled to the semiconductor chip;   a first dielectric layer;   a conductive layer between the semiconductor chip and the first dielectric layer; and   an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip via the conductive layer.   
     
     
         2 . The semiconductor device of  claim 1 , where the antenna is electromagnetically coupled to the semiconductor chip through slots in the conductive layer. 
     
     
         3 . The semiconductor device of  claim 2 , further comprising:
 an encapsulant material laterally surrounding the semiconductor chip.   
     
     
         4 . The semiconductor device of  claim 3 , further comprising:
 where the conductive layer covers the semiconductor chip and the encapsulant material except where the slots are arranged.   
     
     
         5 . The semiconductor device of  claim 1 , further comprising:
 where the antenna includes one or more patch antennas.   
     
     
         6 . The semiconductor device of  claim 1 , the redistribution layer including an RF signal feed, the conductive layer including a slot, where the RF signal feed and the slot are aligned between the antenna and the semiconductor chip to electromagnetically couple the antenna to the semiconductor chip. 
     
     
         7 . The semiconductor device of  claim 1 , comprising:
 a heat sink on a second side of the semiconductor chip opposite to the first side; and   a solder ball coupled to the heat sink.   
     
     
         8 . The semiconductor device of claim  67 , comprising:
 an encapsulation layer surrounding the semiconductor chip, wherein the redistribution layer is coupled to the solder ball through a via in the encapsulation layer.   
     
     
         9 . The semiconductor device of  claim 1 , wherein the antenna comprises a dipole antenna, a folded dipole antenna, a ring antenna, a rectangular loop antenna, a patch antenna, or a coplanar patch antenna. 
     
     
         10 . The semiconductor device of  claim 1 , further comprising:
 an encapsulant material laterally surrounding the semiconductor chip;   wherein the redistribution layer, the conductive layer, and the antenna are on the first side of the semiconductor chip and the encapsulant material.   
     
     
         11 . A semiconductor device comprising:
 a semiconductor chip having a first side and a second side;   a redistribution layer on the first side of the semiconductor chip, the redistribution layer electrically coupled to the semiconductor chip;   a first dielectric layer;   a conductive layer between the semiconductor chip and the first dielectric layer, the conductive layer including a slot; and   an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip through the first slot in the conductive layer.   
     
     
         12 . The semiconductor device of  claim 11 , where the redistribution layer including an RF signal feed. 
     
     
         13 . The semiconductor device of  claim 12 , wherein the first slot and the RF signal feed are aligned between the antenna and the semiconductor chip. 
     
     
         14 . The semiconductor device of  claim 11 , wherein the antenna comprises one or more patch antennas. 
     
     
         15 . The semiconductor device of  claim 11 , comprising:
 a heat sink on the second side of the semiconductor chip opposite to the first side; and   a solder ball coupled to the heat sink.   
     
     
         16 . The semiconductor device of  claim 1 , the heat sink comprising a first heat sink and a second heat sink, where the first heat sink is located directly below the semiconductor chip, and the second heat sink is spaced from the first heat sink. 
     
     
         17 . The semiconductor device of  claim 16 , further comprising:
 an encapsulant material laterally surrounding the semiconductor chip; and   where the redistribution layer is coupled to the second heat sink through a via in the encapsulation material.   
     
     
         18 . The semiconductor device of  claim 11 , wherein the redistribution layer comprises the conductive layer. 
     
     
         19 . The semiconductor device of  claim 11 , comprising a second dielectric layer between the conductive layer and the redistribution layer. 
     
     
         20 . The semiconductor device of  claim 19 , further comprising:
 an encapsulant material laterally surrounding the semiconductor chip; and   a third dielectric layer between the redistribution layer and the encapsulant material and the semiconductor chip.   
     
     
         21 . The semiconductor device of  claim 20 , comprising:
 a fourth dielectric layer on the encapsulant material and semiconductor chip, on the second side of the semiconductor chip opposite the third dielectric material.   
     
     
         22 . The semiconductor device of  claim 11 , comprising one or more contacts located on the semiconductor chip, where the redistributrion layer electrically couples contacts to solder balls through one or more vias located in the encapsulation layer. 
     
     
         23 . The semiconductor device of  claim 11 , where the semiconductor chip is a radio frequency semiconductor chip. 
     
     
         24 . A method for fabricating a semiconductor device package, the method comprising:
 fabricating an embedded wafer level ball grid array package comprising a radio frequency semiconductor chip laterally surrounded by an encapsulant material;   fabricating a redistribution layer on the semiconductor chip and the encapsulant material, the semiconductor chip having a first side and a second side;   fabricating a first dielectric layer;   fabricating a conductive layer between the semiconductor chip and the first dielectric layer, the conductive layer including a slot; and   locating an antenna on the first dielectric layer, where the antenna is electromagnetically coupled to the semiconductor chip through the first slot in the conductive layer.   
     
     
         25 . The method of  claim 24 , comprising fabricating the redistribution layer to include an RF signal feed, and aligning the first slot and the RF signal feed between the antenna and the semiconductor chip. 
     
     
         26 . The method of  claim 25 , comprising:
 providing a carrier; and   attaching the embedded wafer level ball grid array package to the carrier.