Independent double-gate quantum dot qubits

Abstract

Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include a base and a fin extending away from the base and including a quantum well layer. The device may further include a first gate disposed on a first side of the fin and a second gate disposed on a second side of the fin, different from the first side. Providing gates on different sides of a fin advantageously allows increasing the number of quantum dots which may be independently formed and manipulated in the fin. The quantum dots formed in such a device may be constrained in the x-direction by the one or more gates, in the y-direction by the fin, and in the z-direction by the quantum well layer, as discussed in detail herein. Methods for fabricating such devices are also disclosed.

1 . A quantum dot device comprising:
 a fin, comprising a quantum well layer;   first gates over different portions of a first sidewall of the fin;   second gates over different portions of a second sidewall of the fin; and   an insulating material, separating the first gates and the second gates above a top of the fin.   
     
     
         2 . The quantum dot device according to  claim 1 , further comprising:
 an insulating spacer separating gates of each pair of adjacent first gates.   
     
     
         3 . The quantum dot device according to  claim 1 , wherein a distance between a pair of the first gates that are nearest neighbor gates to one another is between 1 and 10 nanometers. 
     
     
         4 . The quantum dot device according to  claim 1 , wherein a dimension of an individual gate of the first gates in a direction parallel to a base from which the fin extends is between 20 and 40 nanometers. 
     
     
         5 . The quantum dot device according to  claim 1 , wherein the fin has a height between 250 and 350 nanometers. 
     
     
         6 . The quantum dot device according to  claim 1 , wherein the fin has a tapered shape that is widest proximate to a bottom of the fin. 
     
     
         7 . The quantum dot device according to  claim 1 , wherein:
 the quantum dot device further includes a base that includes a semiconductor material,   the fin extends away from the base, and   a barrier layer is between the semiconductor material and the quantum well layer.   
     
     
         8 . The quantum dot device according to  claim 1 , further comprising a material stack that includes one or more of silicon and germanium, wherein the quantum well layer is a part of the material stack. 
     
     
         9 . The quantum dot device according to  claim 1 , further comprising a material stack that includes two or more III-V compounds, wherein the quantum well layer is a part of the material stack. 
     
     
         10 . The quantum dot device according to  claim 1 , wherein the insulating material separates the first gates and the second gates so that no portion of the first gates is in contact with any portion of the second gates above the top of the fin. 
     
     
         11 . The quantum dot device according to  claim 1 , wherein:
 the first gates are absent from the top of the fin and the second sidewall of the fin, and   the second gates are absent from the top of the fin and the first sidewall of the fin.   
     
     
         12 . The quantum dot device according to  claim 1 , further comprising a hardmask material over at least a subset of the first gates and the second gates. 
     
     
         13 . The quantum dot device according to  claim 1 , wherein further comprising conductive vias extending to and contacting individual ones of the first gates and the second gates. 
     
     
         14 . A quantum computing device, comprising:
 a quantum processing device, comprising:
 a fin, comprising a quantum well layer, 
 first gates over a first sidewall of the fin, 
 second gates over a second sidewall of the fin, and 
 an insulating material, separating the first gates and the second gates above a top of the fin; 
   a non-quantum processing device, coupled to the quantum processing device, to control voltages applied to at least a subset of the first gates and the second gates during operation of the quantum processing device; and   a memory device, to store data generated during operation of the quantum processing device.   
     
     
         15 . The quantum computing device according to  claim 14 , wherein:
 the quantum well layer includes an active portion and a read portion,   the first gates are closer to the active portion than to the read portion, and   the second gates are closer to the read portion than to the active portion.   
     
     
         16 . The quantum computing device according to  claim 14 , further comprising:
 a cooling apparatus to maintain a temperature of the quantum processing device below 5 degrees Kelvin.   
     
     
         17 . The quantum computing device according to  claim 14 , wherein the memory device is to store instructions for a quantum computing algorithm to be executed by the quantum processing device. 
     
     
         18 . A method of manufacturing a quantum dot device, the method comprising:
 providing a fin, comprising a quantum well layer;   providing first gates over different portions of a first sidewall of the fin;   providing second gates over different portions of a second sidewall of the fin; and   providing an insulating material, separating the first gates and the second gates above a top of the fin.   
     
     
         19 . The method according to  claim 18 , wherein providing the fin includes:
 providing a quantum well stack that includes the quantum well layer, and   removing at least some of the quantum well stack to form the fin that includes the quantum well layer.   
     
     
         20 . The method according to  claim 18 , wherein providing the first gates, the second gates, and the insulating material includes:
 providing the insulating material around the fin,   recessing the insulating material to expose the first sidewall of the fin and the second sidewall of the fin,   forming the first gates and the second gates in portions where the insulating material is recessed.