Display device and electronic device

Abstract

An object of the invention is to provide a circuit technique which enables reduction in power consumption and high definition of a display device. A switch controlled by a start signal is provided to a gate electrode of a transistor, which is connected to a gate electrode of a bootstrap transistor. When the start signal is input, a potential is supplied to the gate electrode of the transistor through the switch, and the transistor is turned off. The transistor is turned off, so that leakage of a charge from the gate electrode of the bootstrap transistor can be prevented. Accordingly, time for storing a charge in the gate electrode of the bootstrap transistor can be shortened, and high-speed operation can be performed.

1 . (canceled) 
     
     
         2 . A semiconductor device comprising:
 a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor,   wherein one of a source and a drain of the first transistor is electrically connected to one of a source and a drain of the second transistor and a first wiring,   wherein one of a source and a drain of the third transistor is electrically connected to one of a source and a drain of the fourth transistor,   wherein one of a source and a drain of the fifth transistor is electrically connected to one of a source and a drain of the sixth transistor,   wherein the other of the source and the drain of the first transistor is electrically connected to a second wiring to which a clock signal is input,   wherein a gate of the first transistor is electrically connected to one of a source and a drain of the seventh transistor,   wherein the other of the source and the drain of the second transistor is electrically connected to the other of the source and the drain of the fourth transistor, the other of the source and the drain of the sixth transistor, one of a source and a drain of the eighth transistor, and a third wiring,   wherein a gate of the second transistor is electrically connected to the one of the source and the drain of the third transistor, the one of the source and the drain of the fourth transistor, a gate of the sixth transistor, and the other of the source and the drain of the eighth transistor,   wherein the other of the source and the drain of the fifth transistor is electrically connected to a fourth wiring,   wherein a gate of the fifth transistor is electrically connected to a fifth wiring,   wherein a gate of the seventh transistor is electrically connected to a sixth wiring,   wherein the semiconductor device further comprises a first conductive layer and a second conductive layer,   wherein the first conductive layer has a first portion functioning as the one of the source and the drain of the third transistor and a second portion functioning as the one of the source and the drain of the fourth transistor, and wherein the second conductive layer comprises a first portion functioning as the other of the source and the drain of the second transistor and a second portion functioning as the other of the source and the drain of the eighth transistor.   
     
     
         3 . The semiconductor device according to  claim 2 , wherein each of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, the sixth transistor, the seventh transistor, and the eighth transistor comprises a polycrystalline semiconductor layer in a channel formation region. 
     
     
         4 . The semiconductor device according to  claim 2 , wherein the first transistor has a multi-gate structure which has a plurality of channel formation regions connected in series.