Device isolation

Abstract

Disclosed herein are structures and techniques for device isolation in integrated circuit (IC) assemblies. In some embodiments, an IC assembly may include multiple transistors spaced apart by an isolation region. The isolation region may include a doped semiconductor body whose dopant concentration is greatest at one or more surfaces, or may include a material that is lattice-mismatched with material of the transistors, for example.

1 . An integrated circuit (IC) assembly, comprising:
 a first transistor including a first portion of a semiconductor body having a first lattice constant;   a second transistor including a second portion of the semiconductor body having a second lattice constant; and   an isolation region between the first portion and the second portion, wherein the isolation region has a third lattice constant different from the first lattice constant and different from the second lattice constant.   
     
     
         2 . The IC assembly of  claim 1 , wherein:
 the first portion of the semiconductor body includes a first epitaxial source/drain region having the first lattice constant, and   the second portion of the semiconductor body includes a second epitaxial source/drain region having the second lattice constant.   
     
     
         3 . The IC assembly of  claim 1 , wherein the first portion of the semiconductor body and the second portion of the semiconductor body include silicon germanium. 
     
     
         4 . The IC assembly of  claim 1 , wherein the first portion of the semiconductor body and the second portion of the semiconductor body include silicon. 
     
     
         5 . The IC assembly of  claim 1 , further comprising:
 an insulating material in contact with one or more surfaces of the isolation region.   
     
     
         6 . The IC assembly of  claim 5 , wherein the insulating material includes silicon oxide. 
     
     
         7 . The IC assembly of  claim 1 , further comprising:
 a substrate, wherein a lattice constant of the substrate is different from the first lattice constant and different from the second lattice constant.   
     
     
         8 . The IC assembly of  claim 1 , wherein a material composition of the first portion is the same as a material composition of the second portion. 
     
     
         9 . The IC assembly of  claim 1 , wherein the third lattice constant is less than the first lattice constant, and less than the second lattice constant. 
     
     
         10 . The IC assembly of  claim 1 , wherein the isolation region includes a p-type dopant. 
     
     
         11 . The IC assembly of  claim 1 , wherein the isolation region includes an n-type dopant. 
     
     
         12 . The IC assembly of  claim 1 , wherein the semiconductor body is a fin. 
     
     
         13 . The IC assembly of  claim 1 , wherein the semiconductor body is a nanowire. 
     
     
         14 . A method of manufacturing an integrated circuit (IC) assembly, the method comprising:
 forming a semiconductor body, wherein the semiconductor body has a first lattice constant;   forming a trench in the semiconductor body; and   providing an insulating material in the trench, wherein the insulating material has a second lattice constant different from the first lattice constant.   
     
     
         15 . The method of  claim 14 , wherein the insulating material includes a semiconductor material. 
     
     
         16 . The method of  claim 14 , wherein the insulating material includes a doped semiconductor material, and wherein a concentration of a dopant in the insulating material is between 5e18 and 1e21. 
     
     
         17 . The method of  claim 14 , further comprising:
 after providing the insulating material in the trench, forming the semiconductor body into one or more fins or nanowires.   
     
     
         18 . A computing device, comprising:
 a die, including:
 a first transistor including a first portion of a semiconductor body having a first lattice constant, 
 a second transistor including a second portion of the semiconductor body having a second lattice constant, and 
 an isolation region between the first portion and the second portion, wherein the isolation region has a third lattice constant different from the first lattice constant and different from the second lattice constant; and 
   a circuit board,   wherein the die is electrically coupled to the circuit board.   
     
     
         19 . The computing device of  claim 18 , wherein the first portion of the semiconductor body is a source/drain region. 
     
     
         20 . The computing device of  claim 18 , further comprising a wireless communications chip.