Integrated schottky diode with guard ring

Abstract

Described examples include an integrated circuit having a semiconductor substrate having an epitaxial layer located thereon, the epitaxial layer having a surface. The integrated circuit also has a buried layer formed in the semiconductor substrate, the epitaxial layer located between the buried layer and the surface. The integrated circuit also has a Schottky contact and an ohmic contact formed on the surface. The integrated circuit also has a Pdrift region in the epitaxial layer located between the ohmic contact and the Schottky contact.

What is claimed is: 
     
         1 . A method of forming an integrated circuit, comprising:
 forming a Schottky contact at a top surface of a semiconductor layer having a first conductivity type; and   forming an ohmic contact to the semiconductor layer; and   forming a first doped region at the top surface between the Schottky contact and the ohmic contact, the first doped region having an opposite second conductivity type and forming a closed path around the Schottky contact.   
     
     
         2 . The method of  claim 1 , further comprising forming a doped buried layer having the first conductivity type between the semiconductor layer and a semiconductor substrate. 
     
     
         3 . The method of  claim 1 , wherein the semiconductor layer includes an N-type epitaxial layer having first doping level. 
     
     
         4 . The method of  claim 1 , further comprising forming a second doped region having the second conductivity type that intersects the surface between the first doped region and the Schottky contact. 
     
     
         5 . The method of  claim 4 , further comprising forming a field plate that extends over the first doped region and the second doped region. 
     
     
         6 . The method of  claim 1 , further comprising forming a dielectric isolation layer over the surface of the semiconductor layer between the ohmic contact and the Schottky contact. 
     
     
         7 . The method of  claim 1 , wherein the first conductivity type is N-type and the second conductivity type is P-type. 
     
     
         8 . The method of  claim 1 , further comprising forming a field plate over the first doped region. 
     
     
         9 . The method of  claim 1 , further including forming an isolation structure that extends from the surface into the semiconductor layer, the isolation structure surrounding the ohmic contact and the Schottky contact. 
     
     
         10 . The method of  claim 1 , further comprising forming a gate layer over the first doped region, and forming a lateral diffused metal-oxide semiconductor (LDMOS) transistor in or over the semiconductor layer, the LDMOS transistor including a gate formed from a same material layer as the gate layer. 
     
     
         11 . A method of forming an integrated circuit, comprising:
 forming an epitaxial layer having a first n-type dopant concentration over a semiconductor substrate, the epitaxial layer having a top surface;   forming an buried layer located between the semiconductor substrate and the epitaxial layer and having a second n-type dopant concentration greater than the first n-type dopant concentration;   forming a doped p-type region located at the top surface, the p-type region surrounding an enclosed portion of the epitaxial layer at the top surface; and   forming a metal silicide at the top surface over the enclosed portion.   
     
     
         12 . The method of  claim 11 , further comprising forming first and second n-type regions at the surface of the epitaxial layer and having a greater dopant concentration than the epitaxial layer, the p-type region and the metal silicide being located between the first and second n-type regions. 
     
     
         13 . The method of  claim 11 , further including forming first and second dielectric isolation layers over the epitaxial layer, the first dielectric isolation layer extending over the p-type region, and the second dielectric isolation layer extending over the p-type region, the metal silicide located between the first and second dielectric isolation layers. 
     
     
         14 . The method of  claim 11 , wherein the p-type region is a first p-type region having a first dopant concentration, and further comprising forming a second p-type region having a greater second dopant concentration located at the surface, an interface between the first p-type region and the epitaxial layer ending at the second p-type region. 
     
     
         15 . The method of  claim 15 , further comprising forming a polysilicon plate over the first p-type region and ending over the second p-type region. 
     
     
         16 . The method of  claim 16 , further comprising forming first and second dielectric isolation layers over the epitaxial layer, the first dielectric isolation layer extending over the first p-type region, and the second dielectric isolation layer extending over the first p-type region, wherein the polysilicon plate ends over the first dielectric isolation layer and over the second dielectric isolation layer. 
     
     
         17 . The method of  claim 16 , further comprising forming a gate dielectric layer between the polysilicon plate and the first p-type region. 
     
     
         18 . A method of forming an electronic device, comprising:
 forming a buried layer in a semiconductor substrate, the buried layer separated from a surface of the semiconductor substrate by a semiconductor layer having a first conductivity type;   forming a Schottky barrier to the semiconductor layer;   forming an ohmic contact to the semiconductor layer; and   forming a doped region having an opposite second conductivity type in the semiconductor layer between the Schottky barrier and the ohmic contact, the doped region completely surrounding the Schottky barrier at the surface.   
     
     
         19 . The method of  claim 19 , further comprising forming an insulating layer on the surface between the Schottky barrier and the ohmic contact, and wherein the insulating layer ends over the doped region. 
     
     
         20 . The method of  claim 20 , wherein the first conductivity type is N-type and the second conductivity type is P-type.