Quantum dot devices with single electron transistor detectors

Abstract

Disclosed herein are quantum dot devices with single electron transistor (SET) detectors. In some embodiments, a quantum dot device may include: a quantum dot formation region; a group of gates disposed on the quantum dot formation region, wherein the group of gates includes at least first, second, and third gates, spacers are disposed on sides of the first and second gates, wherein a first spacer is disposed on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is disposed on a side of the second gate proximate to the first gate, and the third gate is disposed between the first and second gates and extends between the first and second spacers; and a SET disposed on the quantum dot formation region, proximate to the group of gates.

1 . A device, comprising:
 a base;   a fin, extending away from the base and comprising a quantum well stack of a quantum dot device;   a group of gates on a top of the fin and absent from sidewalls of the fin, wherein:
 the group of gates includes at least first, second, and third gates, 
 spacers are on sides of the first and second gates, wherein a first spacer is on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is on a side of the second gate proximate to the first gate, and 
 the third gate is between the first and second gates and extends between the first and second spacers; 
   an insulating material on at least one of the sidewalls of the fin; and   a single electron transistor (SET) on the insulating material, proximate to the group of gates.   
     
     
         2 . The device of  claim 1 , wherein:
 the top of the fin is a surface of the fin that is farthest away from the base, and   the sidewalls of the fin are surfaces of the fin that extend between the top of the fin and the base.   
     
     
         3 . The device of  claim 1 , wherein the fin has a tapered profile that is narrowest proximate to the top surface of the fin. 
     
     
         4 . The device of  claim 1 , wherein the SET includes:
 first and second insulating supports;   first and second source/drain (S/D) electrodes, wherein the first S/D electrode is at a side face of the first insulating support and the second S/D electrode is at a side face of the second insulating support;   an island, between the first and second S/D electrodes and extending into an area between the first and second insulating supports; and   first and second portions of a dielectric, wherein the first portion of the dielectric is between the first S/D electrode and the island, and the second portion of the dielectric is between the second S/D electrode and the island.   
     
     
         5 . The device of  claim 4 , wherein the first and second S/D electrodes are on a substrate, and another portion of the dielectric is between the substrate and the island. 
     
     
         6 . The device of  claim 4 , wherein the SET further includes:
 a third insulating support; and   a gate electrode of the SET at a side face of the third insulating support.   
     
     
         7 . The device of  claim 4 , wherein the SET is a first SET, the island is a first island, the side face of the first insulating support is a first side face of the first insulating support, the side face of the second insulating support is a first side face of the second insulating support, and the device further includes:
 third and fourth S/D electrodes of a second SET, wherein the third S/D electrode is at a second side face of the first insulating support and the fourth S/D electrode is at a second side face of the second insulating support;   a second island of the second SET, between the third and fourth S/D electrodes and extending into the area between the first and second insulating supports; and   third and fourth portions of the dielectric; wherein the third portion of the dielectric is between the third S/D electrode and the second island, and the fourth portion of the dielectric is between the fourth S/D electrode and the second island.   
     
     
         8 . The device of  claim 7 , wherein a third insulating support is between the first and second insulating supports, and the third insulating support is between the first and second islands. 
     
     
         9 . The device of  claim 1 , wherein the SET includes:
 first and second source/drain (S/D) electrodes on a substrate;   an island in an area between the first and second S/D electrodes;   first and second portions of dielectric between the first S/D electrode and the island and between the second S/D electrode and the island, respectively; and   a third portion of dielectric between the substrate and the island.   
     
     
         10 . The device of  claim 1 , wherein:
 the fin is a first fin, the quantum well stack is a first quantum well stack, and the group of gates is a first group of gates,   the device further includes a second fin, parallel to the first fin,   the second fin extends away from the base and includes a second quantum well stack,   the device further includes a second group of gates on a top of the second fin and absent from sidewalls of the second fin, and   the insulating material extends between the at least one of the sidewalls of the first fin and a sidewall of the second fin that is proximate to the first fin.   
     
     
         11 . The device of  claim 10 , wherein a distance between the first fin and the second fin is between 100 and 250 nanometers. 
     
     
         12 . The device of  claim 11 , wherein:
 the device is a quantum computing device, comprising a quantum processing device, a non-quantum processing device, and a memory device,   the quantum computing device includes the base, the fin, the group of gates, the insulating material, and the SET,   the non-quantum processing device is coupled to the quantum processing device and is to control voltages applied to the group of gates and to the SET, and   the memory device is to store data generated by the quantum processing device during operation of the quantum processing device.   
     
     
         13 . A device, comprising:
 a base;   a first fin and a parallel second fin, each extending away from the base and comprising a quantum well stack of a quantum dot device;   a group of gates on a top of the first fin, wherein:
 the group of gates includes at least first, second, and third gates, 
 spacers are on sides of the first and second gates, wherein a first spacer is on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is on a side of the second gate proximate to the first gate, and 
 the third gate is between the first and second gates and extends between the first and second spacers; and 
   an insulating material, extending between, and in contact with, a side of the first fin proximate to the second fin and a side of the second fin proximate to the first fin.   
     
     
         14 . The device of  claim 13 , further including a single electron transistor (SET) on the insulating material, proximate to the group of gates. 
     
     
         15 . The device of  claim 14 , wherein the SET includes:
 first and second source/drain (S/D) electrodes,   an island between the first and second S/D electrodes, and   a gate electrode spaced apart from, and associated with, the island.   
     
     
         16 . The device of  claim 13 , further comprising:
 first and second source/drain (S/D) electrodes of a first single electron transistor (SET) on the insulating material, proximate to the group of gates;   a first island, disposed between the first and second S/D electrodes of the first SET;   a first gate electrode spaced apart from, and associated with, the first island;   first and second S/D electrodes of a second SET on the insulating material, proximate to the group of gates;   a second island, disposed between the first and second S/D electrodes of the second SET;   a second gate electrode spaced apart from, and associated with, the second island.   
     
     
         17 . The device of  claim 16 , wherein the first gate electrode is closer to the first island than to the second island. 
     
     
         18 . The device of  claim 17 , wherein the second gate electrode is closer to the first island than to the second island. 
     
     
         19 . A method of manufacturing a quantum dot device, the method comprising:
 providing a fin, extending away from a base and comprising a quantum well stack of a quantum dot device;   providing a group of gates on a top of the fin and absent from sidewalls of the fin, wherein:
 the group of gates includes at least first, second, and third gates, 
 spacers are on sides of the first and second gates, wherein a first spacer is on a side of the first gate proximate to the second gate, and a second spacer, physically separate from the first spacer, is on a side of the second gate proximate to the first gate, and 
 the third gate is between the first and second gates and extends between the first and second spacers; 
   providing an insulating material on at least one of the sidewalls of the fin; and   providing a single electron transistor (SET) on the insulating material, proximate to the group of gates.   
     
     
         20 . The method of  claim 19 , wherein the SET includes:
 first and second source/drain (S/D) electrodes,   an island between the first and second S/D electrodes, and   a gate electrode spaced apart from, and associated with, the island.