Network On Layer Enabled Architectures

Abstract

The technology relates to a system on chip (SoC). The SoC may include a network on layer including one or more routers and an application specific integrated circuit (ASIC) layer bonded to the network layer, the ASIC layer including one or more components. In some instances, the network layer and the ASIC layer each include an active surface and a second surface opposite the active surface. The active surface of the ASIC layer and the second surface of the network may each include one or more contacts, and the network layer may be bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.

1 . A system on chip (SoC) comprising:
 a first layer including a first component having a first network interface;   a second layer having a second network interface; and   a network layer including one or more routers connected to the first network interface and the second network interface,   wherein the network layer is positioned between the first layer and the second layer, and   wherein the one or more routers are configured to route data between the first layer and the second layer through the network layer.   
     
     
         2 . The system of  claim 1 , wherein the first layer is an application specific integrated circuit (ASIC) layer bonded to the network layer, and wherein the ASIC layer includes at least one component. 
     
     
         3 . The system of  claim 2 , wherein the first network interface connects the at least one component to the one or more routers. 
     
     
         4 . The system of  claim 3 , wherein each of the at least one component is connected to at least one of the one or more routers via one or more conductive structures. 
     
     
         5 . The system of  claim 4 , wherein the conductive structures include one or more of traces, vias, contacts, or terminals. 
     
     
         6 . The system of  claim 2 , wherein the network layer includes:
 an active surface; and   a second surface opposite the active surface.   
     
     
         7 . The system of  claim 6 , wherein the ASIC layer includes:
 an active surface; and   a second surface opposite the active surface.   
     
     
         8 . The system of  claim 7 , wherein the active surface of the ASIC layer and the second surface of the network layer each includes one or more contacts,
 wherein the network layer is bonded to the ASIC layer via bonds formed between the one or more contacts on the second surface of the network layer and the one or more contacts on the active surface of the ASIC layer.   
     
     
         9 . The system of  claim 8 , wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding. 
     
     
         10 . The system of  claim 6 , wherein the second surface of the ASIC layer includes one or more terminals configured to form electrical connections between the SoC with one or more components external to the SoC. 
     
     
         11 . The system of  claim 6 , wherein the second layer is a memory layer including an active surface including one or more contacts. 
     
     
         12 . The system of  claim 11 , wherein the memory layer is bonded to the network layer via bonds formed between one or more contacts on the active surface of the network layer and the one or more contacts on the active surface of the memory layer. 
     
     
         13 . The system of  claim 12 , wherein the bonds are formed via ZiBond direct bonding and/or direct bond interconnect (DBI) hybrid bonding. 
     
     
         14 . The system of  claim 12 , wherein the memory layer includes one or more memory segments. 
     
     
         15 . The system of  claim 14 , wherein the network layer is configured to route data between the at least one component in the ASIC layer and the one or more memory segments. 
     
     
         16 . The system of  claim 14 , wherein each of the one or more memory segments is connected to at least one of the one or more routers in the network layer via one or more conductive structures. 
     
     
         17 . The system of  claim 15 , wherein the network layer is configured to ignore faulty memory segments within the one or more memory segments. 
     
     
         18 . The system of  claim 1 , wherein the network layer includes at least two routers, wherein the at least two routers are connected via one or more routing traces in the network layer. 
     
     
         19 . The system of  claim 1 , wherein the network layer is connected to memory located outside of the SoC. 
     
     
         20 . The system of  claim 2 , wherein the at least one component includes one or more of processors, graphics processing units (GPUs), logic boards, digital sound processors (DSP), or network adaptors.